qemu-e2k/hw/riscv
Alistair Francis ec2c62dacc hw/riscv: boot: Reduce FDT address alignment constraints
We previously stored the device tree at a 16MB alignment from the end of
memory (or 3GB). This means we need at least 16MB of memory to be able
to do this. We don't actually need the FDT to be 16MB aligned, so let's
drop it down to 2MB so that we can support systems with less memory,
while also allowing FDT size expansion.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/992
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20220608062015.317894-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-03 10:03:20 +10:00
..
boot.c hw/riscv: boot: Reduce FDT address alignment constraints 2022-07-03 10:03:20 +10:00
Kconfig hw/riscv: Enable TPM backends 2022-04-29 10:48:48 +10:00
meson.build hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines 2021-07-20 15:32:49 +02:00
microchip_pfsoc.c hw/riscv: Don't add empty bootargs to device tree 2022-04-29 10:47:45 +10:00
numa.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
opentitan.c hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) 2022-05-24 10:38:50 +10:00
riscv_hart.c
shakti_c.c hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id 2021-10-22 23:35:47 +10:00
sifive_e.c hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) 2022-05-24 10:38:50 +10:00
sifive_u.c hw/riscv/sifive_u: Resolve redundant property accessors 2022-05-24 10:38:50 +10:00
spike.c hw/riscv: Make CPU config error handling generous (virt/spike) 2022-05-24 10:38:50 +10:00
virt.c hw/riscv: virt: Generate fw_cfg DT node correctly 2022-06-10 09:31:42 +10:00