7bd1900b36
As the CXLState will no long be accessible via MachineState at time of PXB_CXL realization, come back later from the machine specific code to fill in the missing memory region setup. Only at this stage is it possible to check if cxl=on, so that check is moved to this later point. Note that for multiple host bridges, the allocation order of the register spaces is changed. This will be reflected in ACPI CEDT. Stubs are added to handle case of CONFIG_PXB=n for machines that call these functions. The bus walking logic is common to all machines so add a utility function + stub to cxl-host*. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Message-Id: <20220608145440.26106-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
24 lines
533 B
C
24 lines
533 B
C
/*
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* QEMU CXL Host Setup
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*
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* Copyright (c) 2022 Huawei
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/cxl/cxl.h"
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#include "hw/boards.h"
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#ifndef CXL_HOST_H
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#define CXL_HOST_H
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void cxl_machine_init(Object *obj, CXLState *state);
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void cxl_fmws_link_targets(CXLState *stat, Error **errp);
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void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp);
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extern const MemoryRegionOps cfmws_ops;
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#endif
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