5679479b9a
Opcodes accessing Coprocessor 0 are privileged. Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-28-f4bug@amsat.org>
124 lines
3.7 KiB
C
124 lines
3.7 KiB
C
/*
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* QEMU MIPS CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internal.h"
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#include "exec/exec-all.h"
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/* Called for updates to CP0_Status. */
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void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
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{
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int32_t tcstatus, *tcst;
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uint32_t v = cpu->CP0_Status;
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uint32_t cu, mx, asid, ksu;
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uint32_t mask = ((1 << CP0TCSt_TCU3)
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| (1 << CP0TCSt_TCU2)
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| (1 << CP0TCSt_TCU1)
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| (1 << CP0TCSt_TCU0)
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| (1 << CP0TCSt_TMX)
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| (3 << CP0TCSt_TKSU)
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| (0xff << CP0TCSt_TASID));
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cu = (v >> CP0St_CU0) & 0xf;
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mx = (v >> CP0St_MX) & 0x1;
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ksu = (v >> CP0St_KSU) & 0x3;
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asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
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tcstatus = cu << CP0TCSt_TCU0;
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tcstatus |= mx << CP0TCSt_TMX;
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tcstatus |= ksu << CP0TCSt_TKSU;
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tcstatus |= asid;
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if (tc == cpu->current_tc) {
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tcst = &cpu->active_tc.CP0_TCStatus;
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} else {
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tcst = &cpu->tcs[tc].CP0_TCStatus;
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}
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*tcst &= ~mask;
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*tcst |= tcstatus;
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compute_hflags(cpu);
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}
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void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = env->CP0_Status_rw_bitmask;
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target_ulong old = env->CP0_Status;
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if (env->insn_flags & ISA_MIPS_R6) {
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bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
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#if defined(TARGET_MIPS64)
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uint32_t ksux = (1 << CP0St_KX) & val;
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ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
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ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
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val = (val & ~(7 << CP0St_UX)) | ksux;
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#endif
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if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
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mask &= ~(3 << CP0St_KSU);
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}
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mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
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}
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env->CP0_Status = (old & ~mask) | (val & mask);
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#if defined(TARGET_MIPS64)
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if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
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/* Access to at least one of the 64-bit segments has been disabled */
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tlb_flush(env_cpu(env));
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}
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#endif
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if (ase_mt_available(env)) {
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sync_c0_status(env, env, env->current_tc);
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} else {
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compute_hflags(env);
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}
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}
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void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
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{
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uint32_t mask = 0x00C00300;
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uint32_t old = env->CP0_Cause;
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int i;
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if (env->insn_flags & ISA_MIPS_R2) {
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mask |= 1 << CP0Ca_DC;
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}
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if (env->insn_flags & ISA_MIPS_R6) {
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mask &= ~((1 << CP0Ca_WP) & val);
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}
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env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
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if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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cpu_mips_stop_count(env);
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} else {
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cpu_mips_start_count(env);
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}
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}
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/* Set/reset software interrupts */
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for (i = 0 ; i < 2 ; i++) {
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if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
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cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
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}
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}
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}
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