96e2fc41a9
* hw/sh.h (tmu012_init): Accept qemu_irq, not intc_source.
* hw/sh7750.c (sh7750_init): Pass qemu_irq to tmu012_init.
* hw/sh_intc.c (sh_intc_set_irq): New.
(sh_intc_init): Allocate irqs.
* hw/sh_intc.h (struct intc_desc): New field irqs.
* hw/sh_timer.c (sh_timer_state): Use qemu_irq, not intc_source.
(sh_timer_update): Use qemu_set_irq, not sh_intc_toggle_source.
(sh_timer_init, tmu012_init): Adjust.
(Vladimir Prus)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5768 c046a42c-6fe2-441c-8c8c-71466251a162
464 lines
11 KiB
C
464 lines
11 KiB
C
/*
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* SuperH interrupt controller module
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*
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* Copyright (c) 2007 Magnus Damm
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* Based on sh_timer.c and arm_timer.c by Paul Brook
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* Copyright (c) 2005-2006 CodeSourcery.
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*
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* This code is licenced under the GPL.
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*/
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#include <assert.h>
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#include "sh_intc.h"
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#include "hw.h"
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#include "sh.h"
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//#define DEBUG_INTC
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//#define DEBUG_INTC_SOURCES
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#define INTC_A7(x) ((x) & 0x1fffffff)
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#define INTC_ARRAY(x) (sizeof(x) / sizeof(x[0]))
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void sh_intc_toggle_source(struct intc_source *source,
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int enable_adj, int assert_adj)
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{
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int enable_changed = 0;
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int pending_changed = 0;
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int old_pending;
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if ((source->enable_count == source->enable_max) && (enable_adj == -1))
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enable_changed = -1;
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source->enable_count += enable_adj;
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if (source->enable_count == source->enable_max)
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enable_changed = 1;
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source->asserted += assert_adj;
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old_pending = source->pending;
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source->pending = source->asserted &&
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(source->enable_count == source->enable_max);
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if (old_pending != source->pending)
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pending_changed = 1;
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if (pending_changed) {
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if (source->pending) {
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source->parent->pending++;
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if (source->parent->pending == 1)
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cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
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}
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else {
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source->parent->pending--;
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if (source->parent->pending == 0)
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cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
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}
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}
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if (enable_changed || assert_adj || pending_changed) {
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
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source->parent->pending,
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source->asserted,
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source->enable_count,
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source->enable_max,
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source->vect,
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source->asserted ? "asserted " :
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assert_adj ? "deasserted" : "",
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enable_changed == 1 ? "enabled " :
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enable_changed == -1 ? "disabled " : "",
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source->pending ? "pending" : "");
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#endif
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}
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}
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void sh_intc_set_irq (void *opaque, int n, int level)
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{
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struct intc_desc *desc = opaque;
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struct intc_source *source = &(desc->sources[n]);
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sh_intc_toggle_source(source, 0, level ? 1 : -1);
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}
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int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
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{
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unsigned int i;
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/* slow: use a linked lists of pending sources instead */
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/* wrong: take interrupt priority into account (one list per priority) */
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if (imask == 0x0f) {
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return -1; /* FIXME, update code to include priority per source */
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}
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for (i = 0; i < desc->nr_sources; i++) {
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struct intc_source *source = desc->sources + i;
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if (source->pending) {
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: (%d) returning interrupt source 0x%x\n",
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desc->pending, source->vect);
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#endif
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return source->vect;
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}
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}
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assert(0);
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}
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#define INTC_MODE_NONE 0
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#define INTC_MODE_DUAL_SET 1
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#define INTC_MODE_DUAL_CLR 2
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#define INTC_MODE_ENABLE_REG 3
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#define INTC_MODE_MASK_REG 4
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#define INTC_MODE_IS_PRIO 8
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static unsigned int sh_intc_mode(unsigned long address,
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unsigned long set_reg, unsigned long clr_reg)
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{
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if ((address != INTC_A7(set_reg)) &&
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(address != INTC_A7(clr_reg)))
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return INTC_MODE_NONE;
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if (set_reg && clr_reg) {
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if (address == INTC_A7(set_reg))
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return INTC_MODE_DUAL_SET;
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else
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return INTC_MODE_DUAL_CLR;
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}
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if (set_reg)
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return INTC_MODE_ENABLE_REG;
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else
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return INTC_MODE_MASK_REG;
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}
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static void sh_intc_locate(struct intc_desc *desc,
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unsigned long address,
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unsigned long **datap,
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intc_enum **enums,
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unsigned int *first,
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unsigned int *width,
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unsigned int *modep)
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{
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unsigned int i, mode;
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/* this is slow but works for now */
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if (desc->mask_regs) {
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for (i = 0; i < desc->nr_mask_regs; i++) {
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struct intc_mask_reg *mr = desc->mask_regs + i;
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mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
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if (mode == INTC_MODE_NONE)
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continue;
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*modep = mode;
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*datap = &mr->value;
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*enums = mr->enum_ids;
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*first = mr->reg_width - 1;
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*width = 1;
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return;
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}
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}
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if (desc->prio_regs) {
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for (i = 0; i < desc->nr_prio_regs; i++) {
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struct intc_prio_reg *pr = desc->prio_regs + i;
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mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
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if (mode == INTC_MODE_NONE)
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continue;
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*modep = mode | INTC_MODE_IS_PRIO;
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*datap = &pr->value;
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*enums = pr->enum_ids;
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*first = (pr->reg_width / pr->field_width) - 1;
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*width = pr->field_width;
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return;
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}
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}
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assert(0);
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}
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static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
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int enable, int is_group)
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{
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struct intc_source *source = desc->sources + id;
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if (!id)
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return;
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if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: reserved interrupt source %d modified\n", id);
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#endif
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return;
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}
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if (source->vect)
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sh_intc_toggle_source(source, enable ? 1 : -1, 0);
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#ifdef DEBUG_INTC
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else {
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printf("setting interrupt group %d to %d\n", id, !!enable);
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}
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#endif
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if ((is_group || !source->vect) && source->next_enum_id) {
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sh_intc_toggle_mask(desc, source->next_enum_id, enable, 1);
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}
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#ifdef DEBUG_INTC
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if (!source->vect) {
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printf("setting interrupt group %d to %d - done\n", id, !!enable);
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}
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#endif
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}
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static uint32_t sh_intc_read(void *opaque, target_phys_addr_t offset)
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{
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struct intc_desc *desc = opaque;
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intc_enum *enum_ids = NULL;
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unsigned int first = 0;
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unsigned int width = 0;
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unsigned int mode = 0;
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unsigned long *valuep;
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#ifdef DEBUG_INTC
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printf("sh_intc_read 0x%lx\n", (unsigned long) offset);
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#endif
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sh_intc_locate(desc, (unsigned long)offset, &valuep,
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&enum_ids, &first, &width, &mode);
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return *valuep;
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}
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static void sh_intc_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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struct intc_desc *desc = opaque;
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intc_enum *enum_ids = NULL;
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unsigned int first = 0;
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unsigned int width = 0;
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unsigned int mode = 0;
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unsigned int k;
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unsigned long *valuep;
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unsigned long mask;
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#ifdef DEBUG_INTC
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printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
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#endif
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sh_intc_locate(desc, (unsigned long)offset, &valuep,
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&enum_ids, &first, &width, &mode);
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switch (mode) {
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case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
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case INTC_MODE_DUAL_SET: value |= *valuep; break;
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case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
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default: assert(0);
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}
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for (k = 0; k <= first; k++) {
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mask = ((1 << width) - 1) << ((first - k) * width);
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if ((*valuep & mask) == (value & mask))
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continue;
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#if 0
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printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
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k, first, enum_ids[k], (unsigned int)mask);
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#endif
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sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
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}
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*valuep = value;
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#ifdef DEBUG_INTC
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printf("sh_intc_write 0x%lx -> 0x%08x\n", (unsigned long) offset, value);
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#endif
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}
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static CPUReadMemoryFunc *sh_intc_readfn[] = {
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sh_intc_read,
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sh_intc_read,
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sh_intc_read
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};
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static CPUWriteMemoryFunc *sh_intc_writefn[] = {
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sh_intc_write,
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sh_intc_write,
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sh_intc_write
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};
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struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
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{
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if (id)
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return desc->sources + id;
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return NULL;
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}
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static void sh_intc_register(struct intc_desc *desc,
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unsigned long address)
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{
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if (address)
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cpu_register_physical_memory(INTC_A7(address), 4, desc->iomemtype);
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}
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static void sh_intc_register_source(struct intc_desc *desc,
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intc_enum source,
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struct intc_group *groups,
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int nr_groups)
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{
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unsigned int i, k;
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struct intc_source *s;
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if (desc->mask_regs) {
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for (i = 0; i < desc->nr_mask_regs; i++) {
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struct intc_mask_reg *mr = desc->mask_regs + i;
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for (k = 0; k < INTC_ARRAY(mr->enum_ids); k++) {
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if (mr->enum_ids[k] != source)
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continue;
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s = sh_intc_source(desc, mr->enum_ids[k]);
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if (s)
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s->enable_max++;
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}
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}
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}
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if (desc->prio_regs) {
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for (i = 0; i < desc->nr_prio_regs; i++) {
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struct intc_prio_reg *pr = desc->prio_regs + i;
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for (k = 0; k < INTC_ARRAY(pr->enum_ids); k++) {
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if (pr->enum_ids[k] != source)
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continue;
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s = sh_intc_source(desc, pr->enum_ids[k]);
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if (s)
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s->enable_max++;
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}
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}
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}
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if (groups) {
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for (i = 0; i < nr_groups; i++) {
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struct intc_group *gr = groups + i;
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for (k = 0; k < INTC_ARRAY(gr->enum_ids); k++) {
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if (gr->enum_ids[k] != source)
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continue;
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s = sh_intc_source(desc, gr->enum_ids[k]);
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if (s)
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s->enable_max++;
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}
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}
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}
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}
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void sh_intc_register_sources(struct intc_desc *desc,
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struct intc_vect *vectors,
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int nr_vectors,
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struct intc_group *groups,
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int nr_groups)
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{
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unsigned int i, k;
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struct intc_source *s;
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for (i = 0; i < nr_vectors; i++) {
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struct intc_vect *vect = vectors + i;
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sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
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s = sh_intc_source(desc, vect->enum_id);
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if (s)
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s->vect = vect->vect;
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: registered source %d -> 0x%04x (%d/%d)\n",
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vect->enum_id, s->vect, s->enable_count, s->enable_max);
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#endif
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}
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if (groups) {
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for (i = 0; i < nr_groups; i++) {
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struct intc_group *gr = groups + i;
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s = sh_intc_source(desc, gr->enum_id);
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s->next_enum_id = gr->enum_ids[0];
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for (k = 1; k < INTC_ARRAY(gr->enum_ids); k++) {
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if (!gr->enum_ids[k])
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continue;
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s = sh_intc_source(desc, gr->enum_ids[k - 1]);
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s->next_enum_id = gr->enum_ids[k];
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}
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#ifdef DEBUG_INTC_SOURCES
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printf("sh_intc: registered group %d (%d/%d)\n",
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gr->enum_id, s->enable_count, s->enable_max);
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#endif
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}
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}
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}
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int sh_intc_init(struct intc_desc *desc,
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int nr_sources,
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struct intc_mask_reg *mask_regs,
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int nr_mask_regs,
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struct intc_prio_reg *prio_regs,
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int nr_prio_regs)
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{
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unsigned int i;
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desc->pending = 0;
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desc->nr_sources = nr_sources;
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desc->mask_regs = mask_regs;
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desc->nr_mask_regs = nr_mask_regs;
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desc->prio_regs = prio_regs;
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desc->nr_prio_regs = nr_prio_regs;
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i = sizeof(struct intc_source) * nr_sources;
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desc->sources = malloc(i);
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if (!desc->sources)
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return -1;
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memset(desc->sources, 0, i);
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for (i = 0; i < desc->nr_sources; i++) {
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struct intc_source *source = desc->sources + i;
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source->parent = desc;
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}
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desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources);
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desc->iomemtype = cpu_register_io_memory(0, sh_intc_readfn,
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sh_intc_writefn, desc);
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if (desc->mask_regs) {
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for (i = 0; i < desc->nr_mask_regs; i++) {
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struct intc_mask_reg *mr = desc->mask_regs + i;
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sh_intc_register(desc, mr->set_reg);
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sh_intc_register(desc, mr->clr_reg);
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}
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}
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if (desc->prio_regs) {
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for (i = 0; i < desc->nr_prio_regs; i++) {
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struct intc_prio_reg *pr = desc->prio_regs + i;
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sh_intc_register(desc, pr->set_reg);
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sh_intc_register(desc, pr->clr_reg);
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}
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}
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return 0;
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}
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