Bin Meng 97ba42230b hw/dma: Add SiFive platform DMA controller emulation ... Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution which is actually an IP reused from the SiFive FU540 chip. This creates a model to support both polling and interrupt modes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-09-09 15:54:18 -07:00
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bcm2835_dma.h	hw/arm/bcm283x: Correct the license text	2020-03-23 17:22:30 +00:00
i8257.h	i8257: Move QOM macro to header	2020-08-27 14:04:54 -04:00
pl080.h	hw/dma/pl080: Don't use CPU address space for DMA accesses	2018-08-20 11:24:33 +01:00
sifive_pdma.h	hw/dma: Add SiFive platform DMA controller emulation	2020-09-09 15:54:18 -07:00
xlnx_dpdma.h
xlnx-zdma.h
xlnx-zynq-devcfg.h	Normalize position of header guard	2019-06-12 13:20:20 +02:00