7267c0947d
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
3531 lines
100 KiB
C
3531 lines
100 KiB
C
/**
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* QEMU RTL8139 emulation
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*
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* Copyright (c) 2006 Igor Kovalenko
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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* Modifications:
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* 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
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*
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* 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
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* HW revision ID changes for FreeBSD driver
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*
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* 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
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* Corrected packet transfer reassembly routine for 8139C+ mode
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* Rearranged debugging print statements
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* Implemented PCI timer interrupt (disabled by default)
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* Implemented Tally Counters, increased VM load/save version
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* Implemented IP/TCP/UDP checksum task offloading
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*
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* 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
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* Fixed MTU=1500 for produced ethernet frames
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*
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* 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
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* segmentation offloading
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* Removed slirp.h dependency
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* Added rx/tx buffer reset when enabling rx/tx operation
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*
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* 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
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* when strictly needed (required for for
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* Darwin)
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* 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
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*/
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/* For crc32 */
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#include <zlib.h>
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#include "hw.h"
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#include "pci.h"
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#include "qemu-timer.h"
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#include "net.h"
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#include "loader.h"
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#include "sysemu.h"
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#include "iov.h"
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/* debug RTL8139 card */
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//#define DEBUG_RTL8139 1
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#define PCI_FREQUENCY 33000000L
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/* debug RTL8139 card C+ mode only */
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//#define DEBUG_RTL8139CP 1
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#define SET_MASKED(input, mask, curr) \
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( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
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/* arg % size for size which is a power of 2 */
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#define MOD2(input, size) \
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( ( input ) & ( size - 1 ) )
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#define ETHER_ADDR_LEN 6
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#define ETHER_TYPE_LEN 2
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#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
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#define ETH_P_IP 0x0800 /* Internet Protocol packet */
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#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
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#define ETH_MTU 1500
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#define VLAN_TCI_LEN 2
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#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
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#if defined (DEBUG_RTL8139)
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# define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
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#else
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static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
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{
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return 0;
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}
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#endif
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/* Symbolic offsets to registers. */
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enum RTL8139_registers {
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MAC0 = 0, /* Ethernet hardware address. */
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MAR0 = 8, /* Multicast filter. */
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TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
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/* Dump Tally Conter control register(64bit). C+ mode only */
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TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
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RxBuf = 0x30,
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ChipCmd = 0x37,
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RxBufPtr = 0x38,
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RxBufAddr = 0x3A,
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IntrMask = 0x3C,
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IntrStatus = 0x3E,
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TxConfig = 0x40,
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RxConfig = 0x44,
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Timer = 0x48, /* A general-purpose counter. */
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RxMissed = 0x4C, /* 24 bits valid, write clears. */
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Cfg9346 = 0x50,
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Config0 = 0x51,
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Config1 = 0x52,
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FlashReg = 0x54,
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MediaStatus = 0x58,
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Config3 = 0x59,
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Config4 = 0x5A, /* absent on RTL-8139A */
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HltClk = 0x5B,
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MultiIntr = 0x5C,
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PCIRevisionID = 0x5E,
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TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
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BasicModeCtrl = 0x62,
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BasicModeStatus = 0x64,
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NWayAdvert = 0x66,
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NWayLPAR = 0x68,
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NWayExpansion = 0x6A,
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/* Undocumented registers, but required for proper operation. */
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FIFOTMS = 0x70, /* FIFO Control and test. */
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CSCR = 0x74, /* Chip Status and Configuration Register. */
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PARA78 = 0x78,
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PARA7c = 0x7c, /* Magic transceiver parameter register. */
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Config5 = 0xD8, /* absent on RTL-8139A */
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/* C+ mode */
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TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
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RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
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CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
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IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
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RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
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RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
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TxThresh = 0xEC, /* Early Tx threshold */
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};
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enum ClearBitMasks {
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MultiIntrClear = 0xF000,
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ChipCmdClear = 0xE2,
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Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
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};
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enum ChipCmdBits {
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CmdReset = 0x10,
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CmdRxEnb = 0x08,
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CmdTxEnb = 0x04,
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RxBufEmpty = 0x01,
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};
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/* C+ mode */
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enum CplusCmdBits {
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CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
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CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
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CPlusRxEnb = 0x0002,
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CPlusTxEnb = 0x0001,
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};
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/* Interrupt register bits, using my own meaningful names. */
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enum IntrStatusBits {
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PCIErr = 0x8000,
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PCSTimeout = 0x4000,
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RxFIFOOver = 0x40,
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RxUnderrun = 0x20,
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RxOverflow = 0x10,
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TxErr = 0x08,
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TxOK = 0x04,
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RxErr = 0x02,
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RxOK = 0x01,
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RxAckBits = RxFIFOOver | RxOverflow | RxOK,
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};
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enum TxStatusBits {
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TxHostOwns = 0x2000,
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TxUnderrun = 0x4000,
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TxStatOK = 0x8000,
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TxOutOfWindow = 0x20000000,
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TxAborted = 0x40000000,
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TxCarrierLost = 0x80000000,
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};
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enum RxStatusBits {
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RxMulticast = 0x8000,
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RxPhysical = 0x4000,
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RxBroadcast = 0x2000,
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RxBadSymbol = 0x0020,
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RxRunt = 0x0010,
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RxTooLong = 0x0008,
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RxCRCErr = 0x0004,
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RxBadAlign = 0x0002,
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RxStatusOK = 0x0001,
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};
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/* Bits in RxConfig. */
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enum rx_mode_bits {
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AcceptErr = 0x20,
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AcceptRunt = 0x10,
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AcceptBroadcast = 0x08,
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AcceptMulticast = 0x04,
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AcceptMyPhys = 0x02,
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AcceptAllPhys = 0x01,
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};
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/* Bits in TxConfig. */
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enum tx_config_bits {
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/* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
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TxIFGShift = 24,
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TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
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TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
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TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
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TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
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TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
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TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
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TxClearAbt = (1 << 0), /* Clear abort (WO) */
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TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
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TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
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TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
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};
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/* Transmit Status of All Descriptors (TSAD) Register */
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enum TSAD_bits {
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TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
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TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
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TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
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TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
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TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
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TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
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TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
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TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
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TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
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TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
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TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
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TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
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TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
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TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
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TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
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TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
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};
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/* Bits in Config1 */
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enum Config1Bits {
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Cfg1_PM_Enable = 0x01,
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Cfg1_VPD_Enable = 0x02,
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Cfg1_PIO = 0x04,
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Cfg1_MMIO = 0x08,
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LWAKE = 0x10, /* not on 8139, 8139A */
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Cfg1_Driver_Load = 0x20,
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Cfg1_LED0 = 0x40,
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Cfg1_LED1 = 0x80,
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SLEEP = (1 << 1), /* only on 8139, 8139A */
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PWRDN = (1 << 0), /* only on 8139, 8139A */
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};
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/* Bits in Config3 */
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enum Config3Bits {
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Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
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Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
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Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
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Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
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Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
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Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
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Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
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Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
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};
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/* Bits in Config4 */
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enum Config4Bits {
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LWPTN = (1 << 2), /* not on 8139, 8139A */
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};
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/* Bits in Config5 */
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enum Config5Bits {
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Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
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Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
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Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
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Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
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Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
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Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
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Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
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};
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enum RxConfigBits {
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/* rx fifo threshold */
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RxCfgFIFOShift = 13,
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RxCfgFIFONone = (7 << RxCfgFIFOShift),
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/* Max DMA burst */
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RxCfgDMAShift = 8,
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RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
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/* rx ring buffer length */
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RxCfgRcv8K = 0,
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RxCfgRcv16K = (1 << 11),
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RxCfgRcv32K = (1 << 12),
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RxCfgRcv64K = (1 << 11) | (1 << 12),
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/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
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RxNoWrap = (1 << 7),
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};
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/* Twister tuning parameters from RealTek.
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Completely undocumented, but required to tune bad links on some boards. */
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/*
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enum CSCRBits {
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CSCR_LinkOKBit = 0x0400,
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CSCR_LinkChangeBit = 0x0800,
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CSCR_LinkStatusBits = 0x0f000,
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CSCR_LinkDownOffCmd = 0x003c0,
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CSCR_LinkDownCmd = 0x0f3c0,
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*/
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enum CSCRBits {
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CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
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CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
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CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
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CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
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CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
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CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
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CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
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CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
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CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
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};
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enum Cfg9346Bits {
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Cfg9346_Lock = 0x00,
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Cfg9346_Unlock = 0xC0,
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};
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typedef enum {
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CH_8139 = 0,
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CH_8139_K,
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CH_8139A,
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CH_8139A_G,
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CH_8139B,
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CH_8130,
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CH_8139C,
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CH_8100,
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CH_8100B_8139D,
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CH_8101,
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} chip_t;
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enum chip_flags {
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HasHltClk = (1 << 0),
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HasLWake = (1 << 1),
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};
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#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
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(b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
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#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
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#define RTL8139_PCI_REVID_8139 0x10
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#define RTL8139_PCI_REVID_8139CPLUS 0x20
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#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
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/* Size is 64 * 16bit words */
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#define EEPROM_9346_ADDR_BITS 6
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#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
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#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
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enum Chip9346Operation
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{
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Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
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Chip9346_op_read = 0x80, /* 10 AAAAAA */
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Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
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Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
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Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
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Chip9346_op_write_all = 0x10, /* 00 01zzzz */
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Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
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};
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enum Chip9346Mode
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{
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Chip9346_none = 0,
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Chip9346_enter_command_mode,
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Chip9346_read_command,
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Chip9346_data_read, /* from output register */
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Chip9346_data_write, /* to input register, then to contents at specified address */
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Chip9346_data_write_all, /* to input register, then filling contents */
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};
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typedef struct EEprom9346
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{
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uint16_t contents[EEPROM_9346_SIZE];
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int mode;
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uint32_t tick;
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uint8_t address;
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uint16_t input;
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uint16_t output;
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uint8_t eecs;
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uint8_t eesk;
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uint8_t eedi;
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uint8_t eedo;
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} EEprom9346;
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typedef struct RTL8139TallyCounters
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{
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/* Tally counters */
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uint64_t TxOk;
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uint64_t RxOk;
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uint64_t TxERR;
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uint32_t RxERR;
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uint16_t MissPkt;
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uint16_t FAE;
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uint32_t Tx1Col;
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uint32_t TxMCol;
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uint64_t RxOkPhy;
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uint64_t RxOkBrd;
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uint32_t RxOkMul;
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uint16_t TxAbt;
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uint16_t TxUndrn;
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} RTL8139TallyCounters;
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/* Clears all tally counters */
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static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
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/* Writes tally counters to specified physical memory address */
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static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
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typedef struct RTL8139State {
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PCIDevice dev;
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uint8_t phys[8]; /* mac address */
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uint8_t mult[8]; /* multicast mask array */
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uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
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uint32_t TxAddr[4]; /* TxAddr0 */
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uint32_t RxBuf; /* Receive buffer */
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uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
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uint32_t RxBufPtr;
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|
uint32_t RxBufAddr;
|
|
|
|
uint16_t IntrStatus;
|
|
uint16_t IntrMask;
|
|
|
|
uint32_t TxConfig;
|
|
uint32_t RxConfig;
|
|
uint32_t RxMissed;
|
|
|
|
uint16_t CSCR;
|
|
|
|
uint8_t Cfg9346;
|
|
uint8_t Config0;
|
|
uint8_t Config1;
|
|
uint8_t Config3;
|
|
uint8_t Config4;
|
|
uint8_t Config5;
|
|
|
|
uint8_t clock_enabled;
|
|
uint8_t bChipCmdState;
|
|
|
|
uint16_t MultiIntr;
|
|
|
|
uint16_t BasicModeCtrl;
|
|
uint16_t BasicModeStatus;
|
|
uint16_t NWayAdvert;
|
|
uint16_t NWayLPAR;
|
|
uint16_t NWayExpansion;
|
|
|
|
uint16_t CpCmd;
|
|
uint8_t TxThresh;
|
|
|
|
NICState *nic;
|
|
NICConf conf;
|
|
|
|
/* C ring mode */
|
|
uint32_t currTxDesc;
|
|
|
|
/* C+ mode */
|
|
uint32_t cplus_enabled;
|
|
|
|
uint32_t currCPlusRxDesc;
|
|
uint32_t currCPlusTxDesc;
|
|
|
|
uint32_t RxRingAddrLO;
|
|
uint32_t RxRingAddrHI;
|
|
|
|
EEprom9346 eeprom;
|
|
|
|
uint32_t TCTR;
|
|
uint32_t TimerInt;
|
|
int64_t TCTR_base;
|
|
|
|
/* Tally counters */
|
|
RTL8139TallyCounters tally_counters;
|
|
|
|
/* Non-persistent data */
|
|
uint8_t *cplus_txbuffer;
|
|
int cplus_txbuffer_len;
|
|
int cplus_txbuffer_offset;
|
|
|
|
/* PCI interrupt timer */
|
|
QEMUTimer *timer;
|
|
int64_t TimerExpire;
|
|
|
|
MemoryRegion bar_io;
|
|
MemoryRegion bar_mem;
|
|
|
|
/* Support migration to/from old versions */
|
|
int rtl8139_mmio_io_addr_dummy;
|
|
} RTL8139State;
|
|
|
|
static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
|
|
|
|
static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
|
|
{
|
|
DPRINTF("eeprom command 0x%02x\n", command);
|
|
|
|
switch (command & Chip9346_op_mask)
|
|
{
|
|
case Chip9346_op_read:
|
|
{
|
|
eeprom->address = command & EEPROM_9346_ADDR_MASK;
|
|
eeprom->output = eeprom->contents[eeprom->address];
|
|
eeprom->eedo = 0;
|
|
eeprom->tick = 0;
|
|
eeprom->mode = Chip9346_data_read;
|
|
DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
|
|
eeprom->address, eeprom->output);
|
|
}
|
|
break;
|
|
|
|
case Chip9346_op_write:
|
|
{
|
|
eeprom->address = command & EEPROM_9346_ADDR_MASK;
|
|
eeprom->input = 0;
|
|
eeprom->tick = 0;
|
|
eeprom->mode = Chip9346_none; /* Chip9346_data_write */
|
|
DPRINTF("eeprom begin write to address 0x%02x\n",
|
|
eeprom->address);
|
|
}
|
|
break;
|
|
default:
|
|
eeprom->mode = Chip9346_none;
|
|
switch (command & Chip9346_op_ext_mask)
|
|
{
|
|
case Chip9346_op_write_enable:
|
|
DPRINTF("eeprom write enabled\n");
|
|
break;
|
|
case Chip9346_op_write_all:
|
|
DPRINTF("eeprom begin write all\n");
|
|
break;
|
|
case Chip9346_op_write_disable:
|
|
DPRINTF("eeprom write disabled\n");
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void prom9346_shift_clock(EEprom9346 *eeprom)
|
|
{
|
|
int bit = eeprom->eedi?1:0;
|
|
|
|
++ eeprom->tick;
|
|
|
|
DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
|
|
eeprom->eedo);
|
|
|
|
switch (eeprom->mode)
|
|
{
|
|
case Chip9346_enter_command_mode:
|
|
if (bit)
|
|
{
|
|
eeprom->mode = Chip9346_read_command;
|
|
eeprom->tick = 0;
|
|
eeprom->input = 0;
|
|
DPRINTF("eeprom: +++ synchronized, begin command read\n");
|
|
}
|
|
break;
|
|
|
|
case Chip9346_read_command:
|
|
eeprom->input = (eeprom->input << 1) | (bit & 1);
|
|
if (eeprom->tick == 8)
|
|
{
|
|
prom9346_decode_command(eeprom, eeprom->input & 0xff);
|
|
}
|
|
break;
|
|
|
|
case Chip9346_data_read:
|
|
eeprom->eedo = (eeprom->output & 0x8000)?1:0;
|
|
eeprom->output <<= 1;
|
|
if (eeprom->tick == 16)
|
|
{
|
|
#if 1
|
|
// the FreeBSD drivers (rl and re) don't explicitly toggle
|
|
// CS between reads (or does setting Cfg9346 to 0 count too?),
|
|
// so we need to enter wait-for-command state here
|
|
eeprom->mode = Chip9346_enter_command_mode;
|
|
eeprom->input = 0;
|
|
eeprom->tick = 0;
|
|
|
|
DPRINTF("eeprom: +++ end of read, awaiting next command\n");
|
|
#else
|
|
// original behaviour
|
|
++eeprom->address;
|
|
eeprom->address &= EEPROM_9346_ADDR_MASK;
|
|
eeprom->output = eeprom->contents[eeprom->address];
|
|
eeprom->tick = 0;
|
|
|
|
DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
|
|
eeprom->address, eeprom->output);
|
|
#endif
|
|
}
|
|
break;
|
|
|
|
case Chip9346_data_write:
|
|
eeprom->input = (eeprom->input << 1) | (bit & 1);
|
|
if (eeprom->tick == 16)
|
|
{
|
|
DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
|
|
eeprom->address, eeprom->input);
|
|
|
|
eeprom->contents[eeprom->address] = eeprom->input;
|
|
eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
|
|
eeprom->tick = 0;
|
|
eeprom->input = 0;
|
|
}
|
|
break;
|
|
|
|
case Chip9346_data_write_all:
|
|
eeprom->input = (eeprom->input << 1) | (bit & 1);
|
|
if (eeprom->tick == 16)
|
|
{
|
|
int i;
|
|
for (i = 0; i < EEPROM_9346_SIZE; i++)
|
|
{
|
|
eeprom->contents[i] = eeprom->input;
|
|
}
|
|
DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
|
|
|
|
eeprom->mode = Chip9346_enter_command_mode;
|
|
eeprom->tick = 0;
|
|
eeprom->input = 0;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int prom9346_get_wire(RTL8139State *s)
|
|
{
|
|
EEprom9346 *eeprom = &s->eeprom;
|
|
if (!eeprom->eecs)
|
|
return 0;
|
|
|
|
return eeprom->eedo;
|
|
}
|
|
|
|
/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
|
|
static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
|
|
{
|
|
EEprom9346 *eeprom = &s->eeprom;
|
|
uint8_t old_eecs = eeprom->eecs;
|
|
uint8_t old_eesk = eeprom->eesk;
|
|
|
|
eeprom->eecs = eecs;
|
|
eeprom->eesk = eesk;
|
|
eeprom->eedi = eedi;
|
|
|
|
DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
|
|
eeprom->eesk, eeprom->eedi, eeprom->eedo);
|
|
|
|
if (!old_eecs && eecs)
|
|
{
|
|
/* Synchronize start */
|
|
eeprom->tick = 0;
|
|
eeprom->input = 0;
|
|
eeprom->output = 0;
|
|
eeprom->mode = Chip9346_enter_command_mode;
|
|
|
|
DPRINTF("=== eeprom: begin access, enter command mode\n");
|
|
}
|
|
|
|
if (!eecs)
|
|
{
|
|
DPRINTF("=== eeprom: end access\n");
|
|
return;
|
|
}
|
|
|
|
if (!old_eesk && eesk)
|
|
{
|
|
/* SK front rules */
|
|
prom9346_shift_clock(eeprom);
|
|
}
|
|
}
|
|
|
|
static void rtl8139_update_irq(RTL8139State *s)
|
|
{
|
|
int isr;
|
|
isr = (s->IntrStatus & s->IntrMask) & 0xffff;
|
|
|
|
DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
|
|
s->IntrMask);
|
|
|
|
qemu_set_irq(s->dev.irq[0], (isr != 0));
|
|
}
|
|
|
|
#define POLYNOMIAL 0x04c11db6
|
|
|
|
/* From FreeBSD */
|
|
/* XXX: optimize */
|
|
static int compute_mcast_idx(const uint8_t *ep)
|
|
{
|
|
uint32_t crc;
|
|
int carry, i, j;
|
|
uint8_t b;
|
|
|
|
crc = 0xffffffff;
|
|
for (i = 0; i < 6; i++) {
|
|
b = *ep++;
|
|
for (j = 0; j < 8; j++) {
|
|
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
|
|
crc <<= 1;
|
|
b >>= 1;
|
|
if (carry)
|
|
crc = ((crc ^ POLYNOMIAL) | carry);
|
|
}
|
|
}
|
|
return (crc >> 26);
|
|
}
|
|
|
|
static int rtl8139_RxWrap(RTL8139State *s)
|
|
{
|
|
/* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
|
|
return (s->RxConfig & (1 << 7));
|
|
}
|
|
|
|
static int rtl8139_receiver_enabled(RTL8139State *s)
|
|
{
|
|
return s->bChipCmdState & CmdRxEnb;
|
|
}
|
|
|
|
static int rtl8139_transmitter_enabled(RTL8139State *s)
|
|
{
|
|
return s->bChipCmdState & CmdTxEnb;
|
|
}
|
|
|
|
static int rtl8139_cp_receiver_enabled(RTL8139State *s)
|
|
{
|
|
return s->CpCmd & CPlusRxEnb;
|
|
}
|
|
|
|
static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
|
|
{
|
|
return s->CpCmd & CPlusTxEnb;
|
|
}
|
|
|
|
static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
|
|
{
|
|
if (s->RxBufAddr + size > s->RxBufferSize)
|
|
{
|
|
int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
|
|
|
|
/* write packet data */
|
|
if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
|
|
{
|
|
DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
|
|
|
|
if (size > wrapped)
|
|
{
|
|
cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
|
|
buf, size-wrapped );
|
|
}
|
|
|
|
/* reset buffer pointer */
|
|
s->RxBufAddr = 0;
|
|
|
|
cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
|
|
buf + (size-wrapped), wrapped );
|
|
|
|
s->RxBufAddr = wrapped;
|
|
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* non-wrapping path or overwrapping enabled */
|
|
cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
|
|
|
|
s->RxBufAddr += size;
|
|
}
|
|
|
|
#define MIN_BUF_SIZE 60
|
|
static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
|
|
{
|
|
#if TARGET_PHYS_ADDR_BITS > 32
|
|
return low | ((target_phys_addr_t)high << 32);
|
|
#else
|
|
return low;
|
|
#endif
|
|
}
|
|
|
|
static int rtl8139_can_receive(VLANClientState *nc)
|
|
{
|
|
RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
|
int avail;
|
|
|
|
/* Receive (drop) packets if card is disabled. */
|
|
if (!s->clock_enabled)
|
|
return 1;
|
|
if (!rtl8139_receiver_enabled(s))
|
|
return 1;
|
|
|
|
if (rtl8139_cp_receiver_enabled(s)) {
|
|
/* ??? Flow control not implemented in c+ mode.
|
|
This is a hack to work around slirp deficiencies anyway. */
|
|
return 1;
|
|
} else {
|
|
avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
|
|
s->RxBufferSize);
|
|
return (avail == 0 || avail >= 1514);
|
|
}
|
|
}
|
|
|
|
static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
|
|
{
|
|
RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
|
/* size is the length of the buffer passed to the driver */
|
|
int size = size_;
|
|
const uint8_t *dot1q_buf = NULL;
|
|
|
|
uint32_t packet_header = 0;
|
|
|
|
uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
|
|
static const uint8_t broadcast_macaddr[6] =
|
|
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
|
|
|
DPRINTF(">>> received len=%d\n", size);
|
|
|
|
/* test if board clock is stopped */
|
|
if (!s->clock_enabled)
|
|
{
|
|
DPRINTF("stopped ==========================\n");
|
|
return -1;
|
|
}
|
|
|
|
/* first check if receiver is enabled */
|
|
|
|
if (!rtl8139_receiver_enabled(s))
|
|
{
|
|
DPRINTF("receiver disabled ================\n");
|
|
return -1;
|
|
}
|
|
|
|
/* XXX: check this */
|
|
if (s->RxConfig & AcceptAllPhys) {
|
|
/* promiscuous: receive all */
|
|
DPRINTF(">>> packet received in promiscuous mode\n");
|
|
|
|
} else {
|
|
if (!memcmp(buf, broadcast_macaddr, 6)) {
|
|
/* broadcast address */
|
|
if (!(s->RxConfig & AcceptBroadcast))
|
|
{
|
|
DPRINTF(">>> broadcast packet rejected\n");
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxERR;
|
|
|
|
return size;
|
|
}
|
|
|
|
packet_header |= RxBroadcast;
|
|
|
|
DPRINTF(">>> broadcast packet received\n");
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxOkBrd;
|
|
|
|
} else if (buf[0] & 0x01) {
|
|
/* multicast */
|
|
if (!(s->RxConfig & AcceptMulticast))
|
|
{
|
|
DPRINTF(">>> multicast packet rejected\n");
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxERR;
|
|
|
|
return size;
|
|
}
|
|
|
|
int mcast_idx = compute_mcast_idx(buf);
|
|
|
|
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
|
|
{
|
|
DPRINTF(">>> multicast address mismatch\n");
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxERR;
|
|
|
|
return size;
|
|
}
|
|
|
|
packet_header |= RxMulticast;
|
|
|
|
DPRINTF(">>> multicast packet received\n");
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxOkMul;
|
|
|
|
} else if (s->phys[0] == buf[0] &&
|
|
s->phys[1] == buf[1] &&
|
|
s->phys[2] == buf[2] &&
|
|
s->phys[3] == buf[3] &&
|
|
s->phys[4] == buf[4] &&
|
|
s->phys[5] == buf[5]) {
|
|
/* match */
|
|
if (!(s->RxConfig & AcceptMyPhys))
|
|
{
|
|
DPRINTF(">>> rejecting physical address matching packet\n");
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxERR;
|
|
|
|
return size;
|
|
}
|
|
|
|
packet_header |= RxPhysical;
|
|
|
|
DPRINTF(">>> physical address matching packet received\n");
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxOkPhy;
|
|
|
|
} else {
|
|
|
|
DPRINTF(">>> unknown packet\n");
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxERR;
|
|
|
|
return size;
|
|
}
|
|
}
|
|
|
|
/* if too small buffer, then expand it
|
|
* Include some tailroom in case a vlan tag is later removed. */
|
|
if (size < MIN_BUF_SIZE + VLAN_HLEN) {
|
|
memcpy(buf1, buf, size);
|
|
memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
|
|
buf = buf1;
|
|
if (size < MIN_BUF_SIZE) {
|
|
size = MIN_BUF_SIZE;
|
|
}
|
|
}
|
|
|
|
if (rtl8139_cp_receiver_enabled(s))
|
|
{
|
|
DPRINTF("in C+ Rx mode ================\n");
|
|
|
|
/* begin C+ receiver mode */
|
|
|
|
/* w0 ownership flag */
|
|
#define CP_RX_OWN (1<<31)
|
|
/* w0 end of ring flag */
|
|
#define CP_RX_EOR (1<<30)
|
|
/* w0 bits 0...12 : buffer size */
|
|
#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
|
|
/* w1 tag available flag */
|
|
#define CP_RX_TAVA (1<<16)
|
|
/* w1 bits 0...15 : VLAN tag */
|
|
#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
|
|
/* w2 low 32bit of Rx buffer ptr */
|
|
/* w3 high 32bit of Rx buffer ptr */
|
|
|
|
int descriptor = s->currCPlusRxDesc;
|
|
target_phys_addr_t cplus_rx_ring_desc;
|
|
|
|
cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
|
|
cplus_rx_ring_desc += 16 * descriptor;
|
|
|
|
DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
|
|
"%08x %08x = "TARGET_FMT_plx"\n", descriptor, s->RxRingAddrHI,
|
|
s->RxRingAddrLO, cplus_rx_ring_desc);
|
|
|
|
uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
|
|
|
|
cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
|
rxdw0 = le32_to_cpu(val);
|
|
cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
|
|
rxdw1 = le32_to_cpu(val);
|
|
cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
|
|
rxbufLO = le32_to_cpu(val);
|
|
cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
|
|
rxbufHI = le32_to_cpu(val);
|
|
|
|
DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
|
|
descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
|
|
|
|
if (!(rxdw0 & CP_RX_OWN))
|
|
{
|
|
DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
|
|
descriptor);
|
|
|
|
s->IntrStatus |= RxOverflow;
|
|
++s->RxMissed;
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxERR;
|
|
++s->tally_counters.MissPkt;
|
|
|
|
rtl8139_update_irq(s);
|
|
return size_;
|
|
}
|
|
|
|
uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
|
|
|
|
/* write VLAN info to descriptor variables. */
|
|
if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
|
|
&buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
|
|
dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
|
|
size -= VLAN_HLEN;
|
|
/* if too small buffer, use the tailroom added duing expansion */
|
|
if (size < MIN_BUF_SIZE) {
|
|
size = MIN_BUF_SIZE;
|
|
}
|
|
|
|
rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
|
|
/* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
|
|
rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
|
|
&dot1q_buf[ETHER_TYPE_LEN]);
|
|
|
|
DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
|
|
be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
|
|
} else {
|
|
/* reset VLAN tag flag */
|
|
rxdw1 &= ~CP_RX_TAVA;
|
|
}
|
|
|
|
/* TODO: scatter the packet over available receive ring descriptors space */
|
|
|
|
if (size+4 > rx_space)
|
|
{
|
|
DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
|
|
descriptor, rx_space, size);
|
|
|
|
s->IntrStatus |= RxOverflow;
|
|
++s->RxMissed;
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxERR;
|
|
++s->tally_counters.MissPkt;
|
|
|
|
rtl8139_update_irq(s);
|
|
return size_;
|
|
}
|
|
|
|
target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
|
|
|
|
/* receive/copy to target memory */
|
|
if (dot1q_buf) {
|
|
cpu_physical_memory_write(rx_addr, buf, 2 * ETHER_ADDR_LEN);
|
|
cpu_physical_memory_write(rx_addr + 2 * ETHER_ADDR_LEN,
|
|
buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
|
|
size - 2 * ETHER_ADDR_LEN);
|
|
} else {
|
|
cpu_physical_memory_write(rx_addr, buf, size);
|
|
}
|
|
|
|
if (s->CpCmd & CPlusRxChkSum)
|
|
{
|
|
/* do some packet checksumming */
|
|
}
|
|
|
|
/* write checksum */
|
|
val = cpu_to_le32(crc32(0, buf, size_));
|
|
cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
|
|
|
|
/* first segment of received packet flag */
|
|
#define CP_RX_STATUS_FS (1<<29)
|
|
/* last segment of received packet flag */
|
|
#define CP_RX_STATUS_LS (1<<28)
|
|
/* multicast packet flag */
|
|
#define CP_RX_STATUS_MAR (1<<26)
|
|
/* physical-matching packet flag */
|
|
#define CP_RX_STATUS_PAM (1<<25)
|
|
/* broadcast packet flag */
|
|
#define CP_RX_STATUS_BAR (1<<24)
|
|
/* runt packet flag */
|
|
#define CP_RX_STATUS_RUNT (1<<19)
|
|
/* crc error flag */
|
|
#define CP_RX_STATUS_CRC (1<<18)
|
|
/* IP checksum error flag */
|
|
#define CP_RX_STATUS_IPF (1<<15)
|
|
/* UDP checksum error flag */
|
|
#define CP_RX_STATUS_UDPF (1<<14)
|
|
/* TCP checksum error flag */
|
|
#define CP_RX_STATUS_TCPF (1<<13)
|
|
|
|
/* transfer ownership to target */
|
|
rxdw0 &= ~CP_RX_OWN;
|
|
|
|
/* set first segment bit */
|
|
rxdw0 |= CP_RX_STATUS_FS;
|
|
|
|
/* set last segment bit */
|
|
rxdw0 |= CP_RX_STATUS_LS;
|
|
|
|
/* set received packet type flags */
|
|
if (packet_header & RxBroadcast)
|
|
rxdw0 |= CP_RX_STATUS_BAR;
|
|
if (packet_header & RxMulticast)
|
|
rxdw0 |= CP_RX_STATUS_MAR;
|
|
if (packet_header & RxPhysical)
|
|
rxdw0 |= CP_RX_STATUS_PAM;
|
|
|
|
/* set received size */
|
|
rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
|
|
rxdw0 |= (size+4);
|
|
|
|
/* update ring data */
|
|
val = cpu_to_le32(rxdw0);
|
|
cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
|
|
val = cpu_to_le32(rxdw1);
|
|
cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.RxOk;
|
|
|
|
/* seek to next Rx descriptor */
|
|
if (rxdw0 & CP_RX_EOR)
|
|
{
|
|
s->currCPlusRxDesc = 0;
|
|
}
|
|
else
|
|
{
|
|
++s->currCPlusRxDesc;
|
|
}
|
|
|
|
DPRINTF("done C+ Rx mode ----------------\n");
|
|
|
|
}
|
|
else
|
|
{
|
|
DPRINTF("in ring Rx mode ================\n");
|
|
|
|
/* begin ring receiver mode */
|
|
int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
|
|
|
|
/* if receiver buffer is empty then avail == 0 */
|
|
|
|
if (avail != 0 && size + 8 >= avail)
|
|
{
|
|
DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
|
|
"read 0x%04x === available 0x%04x need 0x%04x\n",
|
|
s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
|
|
|
|
s->IntrStatus |= RxOverflow;
|
|
++s->RxMissed;
|
|
rtl8139_update_irq(s);
|
|
return size_;
|
|
}
|
|
|
|
packet_header |= RxStatusOK;
|
|
|
|
packet_header |= (((size+4) << 16) & 0xffff0000);
|
|
|
|
/* write header */
|
|
uint32_t val = cpu_to_le32(packet_header);
|
|
|
|
rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
|
|
|
rtl8139_write_buffer(s, buf, size);
|
|
|
|
/* write checksum */
|
|
val = cpu_to_le32(crc32(0, buf, size));
|
|
rtl8139_write_buffer(s, (uint8_t *)&val, 4);
|
|
|
|
/* correct buffer write pointer */
|
|
s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
|
|
|
|
/* now we can signal we have received something */
|
|
|
|
DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
|
|
s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
|
|
}
|
|
|
|
s->IntrStatus |= RxOK;
|
|
|
|
if (do_interrupt)
|
|
{
|
|
rtl8139_update_irq(s);
|
|
}
|
|
|
|
return size_;
|
|
}
|
|
|
|
static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
|
|
{
|
|
return rtl8139_do_receive(nc, buf, size, 1);
|
|
}
|
|
|
|
static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
|
|
{
|
|
s->RxBufferSize = bufferSize;
|
|
s->RxBufPtr = 0;
|
|
s->RxBufAddr = 0;
|
|
}
|
|
|
|
static void rtl8139_reset(DeviceState *d)
|
|
{
|
|
RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
|
|
int i;
|
|
|
|
/* restore MAC address */
|
|
memcpy(s->phys, s->conf.macaddr.a, 6);
|
|
|
|
/* reset interrupt mask */
|
|
s->IntrStatus = 0;
|
|
s->IntrMask = 0;
|
|
|
|
rtl8139_update_irq(s);
|
|
|
|
/* mark all status registers as owned by host */
|
|
for (i = 0; i < 4; ++i)
|
|
{
|
|
s->TxStatus[i] = TxHostOwns;
|
|
}
|
|
|
|
s->currTxDesc = 0;
|
|
s->currCPlusRxDesc = 0;
|
|
s->currCPlusTxDesc = 0;
|
|
|
|
s->RxRingAddrLO = 0;
|
|
s->RxRingAddrHI = 0;
|
|
|
|
s->RxBuf = 0;
|
|
|
|
rtl8139_reset_rxring(s, 8192);
|
|
|
|
/* ACK the reset */
|
|
s->TxConfig = 0;
|
|
|
|
#if 0
|
|
// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
|
|
s->clock_enabled = 0;
|
|
#else
|
|
s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
|
|
s->clock_enabled = 1;
|
|
#endif
|
|
|
|
s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
|
|
|
|
/* set initial state data */
|
|
s->Config0 = 0x0; /* No boot ROM */
|
|
s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
|
|
s->Config3 = 0x1; /* fast back-to-back compatible */
|
|
s->Config5 = 0x0;
|
|
|
|
s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
|
|
|
|
s->CpCmd = 0x0; /* reset C+ mode */
|
|
s->cplus_enabled = 0;
|
|
|
|
|
|
// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
|
|
// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
|
|
s->BasicModeCtrl = 0x1000; // autonegotiation
|
|
|
|
s->BasicModeStatus = 0x7809;
|
|
//s->BasicModeStatus |= 0x0040; /* UTP medium */
|
|
s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
|
|
s->BasicModeStatus |= 0x0004; /* link is up */
|
|
|
|
s->NWayAdvert = 0x05e1; /* all modes, full duplex */
|
|
s->NWayLPAR = 0x05e1; /* all modes, full duplex */
|
|
s->NWayExpansion = 0x0001; /* autonegotiation supported */
|
|
|
|
/* also reset timer and disable timer interrupt */
|
|
s->TCTR = 0;
|
|
s->TimerInt = 0;
|
|
s->TCTR_base = 0;
|
|
|
|
/* reset tally counters */
|
|
RTL8139TallyCounters_clear(&s->tally_counters);
|
|
}
|
|
|
|
static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
|
|
{
|
|
counters->TxOk = 0;
|
|
counters->RxOk = 0;
|
|
counters->TxERR = 0;
|
|
counters->RxERR = 0;
|
|
counters->MissPkt = 0;
|
|
counters->FAE = 0;
|
|
counters->Tx1Col = 0;
|
|
counters->TxMCol = 0;
|
|
counters->RxOkPhy = 0;
|
|
counters->RxOkBrd = 0;
|
|
counters->RxOkMul = 0;
|
|
counters->TxAbt = 0;
|
|
counters->TxUndrn = 0;
|
|
}
|
|
|
|
static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
|
|
{
|
|
uint16_t val16;
|
|
uint32_t val32;
|
|
uint64_t val64;
|
|
|
|
val64 = cpu_to_le64(tally_counters->TxOk);
|
|
cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
|
|
|
|
val64 = cpu_to_le64(tally_counters->RxOk);
|
|
cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
|
|
|
|
val64 = cpu_to_le64(tally_counters->TxERR);
|
|
cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
|
|
|
|
val32 = cpu_to_le32(tally_counters->RxERR);
|
|
cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
|
|
|
|
val16 = cpu_to_le16(tally_counters->MissPkt);
|
|
cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
|
|
|
|
val16 = cpu_to_le16(tally_counters->FAE);
|
|
cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
|
|
|
|
val32 = cpu_to_le32(tally_counters->Tx1Col);
|
|
cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
|
|
|
|
val32 = cpu_to_le32(tally_counters->TxMCol);
|
|
cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
|
|
|
|
val64 = cpu_to_le64(tally_counters->RxOkPhy);
|
|
cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
|
|
|
|
val64 = cpu_to_le64(tally_counters->RxOkBrd);
|
|
cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
|
|
|
|
val32 = cpu_to_le32(tally_counters->RxOkMul);
|
|
cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
|
|
|
|
val16 = cpu_to_le16(tally_counters->TxAbt);
|
|
cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
|
|
|
|
val16 = cpu_to_le16(tally_counters->TxUndrn);
|
|
cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
|
|
}
|
|
|
|
/* Loads values of tally counters from VM state file */
|
|
|
|
static const VMStateDescription vmstate_tally_counters = {
|
|
.name = "tally_counters",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
|
|
VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
|
|
VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
|
|
VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
|
|
VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
|
|
VMSTATE_UINT16(FAE, RTL8139TallyCounters),
|
|
VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
|
|
VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
|
|
VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
|
|
VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
|
|
VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
|
|
VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xff;
|
|
|
|
DPRINTF("ChipCmd write val=0x%08x\n", val);
|
|
|
|
if (val & CmdReset)
|
|
{
|
|
DPRINTF("ChipCmd reset\n");
|
|
rtl8139_reset(&s->dev.qdev);
|
|
}
|
|
if (val & CmdRxEnb)
|
|
{
|
|
DPRINTF("ChipCmd enable receiver\n");
|
|
|
|
s->currCPlusRxDesc = 0;
|
|
}
|
|
if (val & CmdTxEnb)
|
|
{
|
|
DPRINTF("ChipCmd enable transmitter\n");
|
|
|
|
s->currCPlusTxDesc = 0;
|
|
}
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0xe3, s->bChipCmdState);
|
|
|
|
/* Deassert reset pin before next read */
|
|
val &= ~CmdReset;
|
|
|
|
s->bChipCmdState = val;
|
|
}
|
|
|
|
static int rtl8139_RxBufferEmpty(RTL8139State *s)
|
|
{
|
|
int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
|
|
|
|
if (unread != 0)
|
|
{
|
|
DPRINTF("receiver buffer data available 0x%04x\n", unread);
|
|
return 0;
|
|
}
|
|
|
|
DPRINTF("receiver buffer is empty\n");
|
|
|
|
return 1;
|
|
}
|
|
|
|
static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->bChipCmdState;
|
|
|
|
if (rtl8139_RxBufferEmpty(s))
|
|
ret |= RxBufEmpty;
|
|
|
|
DPRINTF("ChipCmd read val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xffff;
|
|
|
|
DPRINTF("C+ command register write(w) val=0x%04x\n", val);
|
|
|
|
s->cplus_enabled = 1;
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0xff84, s->CpCmd);
|
|
|
|
s->CpCmd = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->CpCmd;
|
|
|
|
DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
|
|
}
|
|
|
|
static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = 0;
|
|
|
|
DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rtl8139_config_writable(RTL8139State *s)
|
|
{
|
|
if (s->Cfg9346 & Cfg9346_Unlock)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
DPRINTF("Configuration registers are write-protected\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xffff;
|
|
|
|
DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
|
|
|
|
/* mask unwritable bits */
|
|
uint32_t mask = 0x4cff;
|
|
|
|
if (1 || !rtl8139_config_writable(s))
|
|
{
|
|
/* Speed setting and autonegotiation enable bits are read-only */
|
|
mask |= 0x3000;
|
|
/* Duplex mode setting is read-only */
|
|
mask |= 0x0100;
|
|
}
|
|
|
|
val = SET_MASKED(val, mask, s->BasicModeCtrl);
|
|
|
|
s->BasicModeCtrl = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->BasicModeCtrl;
|
|
|
|
DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xffff;
|
|
|
|
DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
|
|
|
|
s->BasicModeStatus = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->BasicModeStatus;
|
|
|
|
DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xff;
|
|
|
|
DPRINTF("Cfg9346 write val=0x%02x\n", val);
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0x31, s->Cfg9346);
|
|
|
|
uint32_t opmode = val & 0xc0;
|
|
uint32_t eeprom_val = val & 0xf;
|
|
|
|
if (opmode == 0x80) {
|
|
/* eeprom access */
|
|
int eecs = (eeprom_val & 0x08)?1:0;
|
|
int eesk = (eeprom_val & 0x04)?1:0;
|
|
int eedi = (eeprom_val & 0x02)?1:0;
|
|
prom9346_set_wire(s, eecs, eesk, eedi);
|
|
} else if (opmode == 0x40) {
|
|
/* Reset. */
|
|
val = 0;
|
|
rtl8139_reset(&s->dev.qdev);
|
|
}
|
|
|
|
s->Cfg9346 = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->Cfg9346;
|
|
|
|
uint32_t opmode = ret & 0xc0;
|
|
|
|
if (opmode == 0x80)
|
|
{
|
|
/* eeprom access */
|
|
int eedo = prom9346_get_wire(s);
|
|
if (eedo)
|
|
{
|
|
ret |= 0x01;
|
|
}
|
|
else
|
|
{
|
|
ret &= ~0x01;
|
|
}
|
|
}
|
|
|
|
DPRINTF("Cfg9346 read val=0x%02x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xff;
|
|
|
|
DPRINTF("Config0 write val=0x%02x\n", val);
|
|
|
|
if (!rtl8139_config_writable(s)) {
|
|
return;
|
|
}
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0xf8, s->Config0);
|
|
|
|
s->Config0 = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_Config0_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->Config0;
|
|
|
|
DPRINTF("Config0 read val=0x%02x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xff;
|
|
|
|
DPRINTF("Config1 write val=0x%02x\n", val);
|
|
|
|
if (!rtl8139_config_writable(s)) {
|
|
return;
|
|
}
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0xC, s->Config1);
|
|
|
|
s->Config1 = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_Config1_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->Config1;
|
|
|
|
DPRINTF("Config1 read val=0x%02x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xff;
|
|
|
|
DPRINTF("Config3 write val=0x%02x\n", val);
|
|
|
|
if (!rtl8139_config_writable(s)) {
|
|
return;
|
|
}
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0x8F, s->Config3);
|
|
|
|
s->Config3 = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_Config3_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->Config3;
|
|
|
|
DPRINTF("Config3 read val=0x%02x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xff;
|
|
|
|
DPRINTF("Config4 write val=0x%02x\n", val);
|
|
|
|
if (!rtl8139_config_writable(s)) {
|
|
return;
|
|
}
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0x0a, s->Config4);
|
|
|
|
s->Config4 = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_Config4_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->Config4;
|
|
|
|
DPRINTF("Config4 read val=0x%02x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
val &= 0xff;
|
|
|
|
DPRINTF("Config5 write val=0x%02x\n", val);
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0x80, s->Config5);
|
|
|
|
s->Config5 = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_Config5_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->Config5;
|
|
|
|
DPRINTF("Config5 read val=0x%02x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
if (!rtl8139_transmitter_enabled(s))
|
|
{
|
|
DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
|
|
return;
|
|
}
|
|
|
|
DPRINTF("TxConfig write val=0x%08x\n", val);
|
|
|
|
val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
|
|
|
|
s->TxConfig = val;
|
|
}
|
|
|
|
static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
|
|
{
|
|
DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
|
|
|
|
uint32_t tc = s->TxConfig;
|
|
tc &= 0xFFFFFF00;
|
|
tc |= (val & 0x000000FF);
|
|
rtl8139_TxConfig_write(s, tc);
|
|
}
|
|
|
|
static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->TxConfig;
|
|
|
|
DPRINTF("TxConfig read val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
DPRINTF("RxConfig write val=0x%08x\n", val);
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
|
|
|
|
s->RxConfig = val;
|
|
|
|
/* reset buffer size and read/write pointers */
|
|
rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
|
|
|
|
DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
|
|
}
|
|
|
|
static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->RxConfig;
|
|
|
|
DPRINTF("RxConfig read val=0x%08x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
|
|
int do_interrupt, const uint8_t *dot1q_buf)
|
|
{
|
|
struct iovec *iov = NULL;
|
|
|
|
if (!size)
|
|
{
|
|
DPRINTF("+++ empty ethernet frame\n");
|
|
return;
|
|
}
|
|
|
|
if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
|
|
iov = (struct iovec[3]) {
|
|
{ .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
|
|
{ .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
|
|
{ .iov_base = buf + ETHER_ADDR_LEN * 2,
|
|
.iov_len = size - ETHER_ADDR_LEN * 2 },
|
|
};
|
|
}
|
|
|
|
if (TxLoopBack == (s->TxConfig & TxLoopBack))
|
|
{
|
|
size_t buf2_size;
|
|
uint8_t *buf2;
|
|
|
|
if (iov) {
|
|
buf2_size = iov_size(iov, 3);
|
|
buf2 = g_malloc(buf2_size);
|
|
iov_to_buf(iov, 3, buf2, 0, buf2_size);
|
|
buf = buf2;
|
|
}
|
|
|
|
DPRINTF("+++ transmit loopback mode\n");
|
|
rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
|
|
|
|
if (iov) {
|
|
g_free(buf2);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (iov) {
|
|
qemu_sendv_packet(&s->nic->nc, iov, 3);
|
|
} else {
|
|
qemu_send_packet(&s->nic->nc, buf, size);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
|
|
{
|
|
if (!rtl8139_transmitter_enabled(s))
|
|
{
|
|
DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
|
|
"disabled\n", descriptor);
|
|
return 0;
|
|
}
|
|
|
|
if (s->TxStatus[descriptor] & TxHostOwns)
|
|
{
|
|
DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
|
|
"(%08x)\n", descriptor, s->TxStatus[descriptor]);
|
|
return 0;
|
|
}
|
|
|
|
DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
|
|
|
|
int txsize = s->TxStatus[descriptor] & 0x1fff;
|
|
uint8_t txbuffer[0x2000];
|
|
|
|
DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
|
|
txsize, s->TxAddr[descriptor]);
|
|
|
|
cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
|
|
|
|
/* Mark descriptor as transferred */
|
|
s->TxStatus[descriptor] |= TxHostOwns;
|
|
s->TxStatus[descriptor] |= TxStatOK;
|
|
|
|
rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
|
|
|
|
DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
|
|
descriptor);
|
|
|
|
/* update interrupt */
|
|
s->IntrStatus |= TxOK;
|
|
rtl8139_update_irq(s);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/* structures and macros for task offloading */
|
|
typedef struct ip_header
|
|
{
|
|
uint8_t ip_ver_len; /* version and header length */
|
|
uint8_t ip_tos; /* type of service */
|
|
uint16_t ip_len; /* total length */
|
|
uint16_t ip_id; /* identification */
|
|
uint16_t ip_off; /* fragment offset field */
|
|
uint8_t ip_ttl; /* time to live */
|
|
uint8_t ip_p; /* protocol */
|
|
uint16_t ip_sum; /* checksum */
|
|
uint32_t ip_src,ip_dst; /* source and dest address */
|
|
} ip_header;
|
|
|
|
#define IP_HEADER_VERSION_4 4
|
|
#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
|
|
#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
|
|
|
|
typedef struct tcp_header
|
|
{
|
|
uint16_t th_sport; /* source port */
|
|
uint16_t th_dport; /* destination port */
|
|
uint32_t th_seq; /* sequence number */
|
|
uint32_t th_ack; /* acknowledgement number */
|
|
uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
|
|
uint16_t th_win; /* window */
|
|
uint16_t th_sum; /* checksum */
|
|
uint16_t th_urp; /* urgent pointer */
|
|
} tcp_header;
|
|
|
|
typedef struct udp_header
|
|
{
|
|
uint16_t uh_sport; /* source port */
|
|
uint16_t uh_dport; /* destination port */
|
|
uint16_t uh_ulen; /* udp length */
|
|
uint16_t uh_sum; /* udp checksum */
|
|
} udp_header;
|
|
|
|
typedef struct ip_pseudo_header
|
|
{
|
|
uint32_t ip_src;
|
|
uint32_t ip_dst;
|
|
uint8_t zeros;
|
|
uint8_t ip_proto;
|
|
uint16_t ip_payload;
|
|
} ip_pseudo_header;
|
|
|
|
#define IP_PROTO_TCP 6
|
|
#define IP_PROTO_UDP 17
|
|
|
|
#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
|
|
#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
|
|
#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
|
|
|
|
#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
|
|
|
|
#define TCP_FLAG_FIN 0x01
|
|
#define TCP_FLAG_PUSH 0x08
|
|
|
|
/* produces ones' complement sum of data */
|
|
static uint16_t ones_complement_sum(uint8_t *data, size_t len)
|
|
{
|
|
uint32_t result = 0;
|
|
|
|
for (; len > 1; data+=2, len-=2)
|
|
{
|
|
result += *(uint16_t*)data;
|
|
}
|
|
|
|
/* add the remainder byte */
|
|
if (len)
|
|
{
|
|
uint8_t odd[2] = {*data, 0};
|
|
result += *(uint16_t*)odd;
|
|
}
|
|
|
|
while (result>>16)
|
|
result = (result & 0xffff) + (result >> 16);
|
|
|
|
return result;
|
|
}
|
|
|
|
static uint16_t ip_checksum(void *data, size_t len)
|
|
{
|
|
return ~ones_complement_sum((uint8_t*)data, len);
|
|
}
|
|
|
|
static int rtl8139_cplus_transmit_one(RTL8139State *s)
|
|
{
|
|
if (!rtl8139_transmitter_enabled(s))
|
|
{
|
|
DPRINTF("+++ C+ mode: transmitter disabled\n");
|
|
return 0;
|
|
}
|
|
|
|
if (!rtl8139_cp_transmitter_enabled(s))
|
|
{
|
|
DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
|
|
return 0 ;
|
|
}
|
|
|
|
int descriptor = s->currCPlusTxDesc;
|
|
|
|
target_phys_addr_t cplus_tx_ring_desc =
|
|
rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
|
|
|
|
/* Normal priority ring */
|
|
cplus_tx_ring_desc += 16 * descriptor;
|
|
|
|
DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
|
|
"%08x0x%08x = 0x"TARGET_FMT_plx"\n", descriptor, s->TxAddr[1],
|
|
s->TxAddr[0], cplus_tx_ring_desc);
|
|
|
|
uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
|
|
|
|
cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
|
txdw0 = le32_to_cpu(val);
|
|
cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
|
|
txdw1 = le32_to_cpu(val);
|
|
cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
|
|
txbufLO = le32_to_cpu(val);
|
|
cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
|
|
txbufHI = le32_to_cpu(val);
|
|
|
|
DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
|
|
txdw0, txdw1, txbufLO, txbufHI);
|
|
|
|
/* w0 ownership flag */
|
|
#define CP_TX_OWN (1<<31)
|
|
/* w0 end of ring flag */
|
|
#define CP_TX_EOR (1<<30)
|
|
/* first segment of received packet flag */
|
|
#define CP_TX_FS (1<<29)
|
|
/* last segment of received packet flag */
|
|
#define CP_TX_LS (1<<28)
|
|
/* large send packet flag */
|
|
#define CP_TX_LGSEN (1<<27)
|
|
/* large send MSS mask, bits 16...25 */
|
|
#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
|
|
|
|
/* IP checksum offload flag */
|
|
#define CP_TX_IPCS (1<<18)
|
|
/* UDP checksum offload flag */
|
|
#define CP_TX_UDPCS (1<<17)
|
|
/* TCP checksum offload flag */
|
|
#define CP_TX_TCPCS (1<<16)
|
|
|
|
/* w0 bits 0...15 : buffer size */
|
|
#define CP_TX_BUFFER_SIZE (1<<16)
|
|
#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
|
|
/* w1 add tag flag */
|
|
#define CP_TX_TAGC (1<<17)
|
|
/* w1 bits 0...15 : VLAN tag (big endian) */
|
|
#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
|
|
/* w2 low 32bit of Rx buffer ptr */
|
|
/* w3 high 32bit of Rx buffer ptr */
|
|
|
|
/* set after transmission */
|
|
/* FIFO underrun flag */
|
|
#define CP_TX_STATUS_UNF (1<<25)
|
|
/* transmit error summary flag, valid if set any of three below */
|
|
#define CP_TX_STATUS_TES (1<<23)
|
|
/* out-of-window collision flag */
|
|
#define CP_TX_STATUS_OWC (1<<22)
|
|
/* link failure flag */
|
|
#define CP_TX_STATUS_LNKF (1<<21)
|
|
/* excessive collisions flag */
|
|
#define CP_TX_STATUS_EXC (1<<20)
|
|
|
|
if (!(txdw0 & CP_TX_OWN))
|
|
{
|
|
DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
|
|
return 0 ;
|
|
}
|
|
|
|
DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
|
|
|
|
if (txdw0 & CP_TX_FS)
|
|
{
|
|
DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
|
|
"descriptor\n", descriptor);
|
|
|
|
/* reset internal buffer offset */
|
|
s->cplus_txbuffer_offset = 0;
|
|
}
|
|
|
|
int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
|
|
target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
|
|
|
|
/* make sure we have enough space to assemble the packet */
|
|
if (!s->cplus_txbuffer)
|
|
{
|
|
s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
|
|
s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
|
|
s->cplus_txbuffer_offset = 0;
|
|
|
|
DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
|
|
s->cplus_txbuffer_len);
|
|
}
|
|
|
|
while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
|
|
{
|
|
s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
|
|
s->cplus_txbuffer = g_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
|
|
|
|
DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
|
|
s->cplus_txbuffer_len);
|
|
}
|
|
|
|
if (!s->cplus_txbuffer)
|
|
{
|
|
/* out of memory */
|
|
|
|
DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
|
|
s->cplus_txbuffer_len);
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.TxERR;
|
|
++s->tally_counters.TxAbt;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* append more data to the packet */
|
|
|
|
DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
|
|
TARGET_FMT_plx" to offset %d\n", txsize, tx_addr,
|
|
s->cplus_txbuffer_offset);
|
|
|
|
cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
|
|
s->cplus_txbuffer_offset += txsize;
|
|
|
|
/* seek to next Rx descriptor */
|
|
if (txdw0 & CP_TX_EOR)
|
|
{
|
|
s->currCPlusTxDesc = 0;
|
|
}
|
|
else
|
|
{
|
|
++s->currCPlusTxDesc;
|
|
if (s->currCPlusTxDesc >= 64)
|
|
s->currCPlusTxDesc = 0;
|
|
}
|
|
|
|
/* transfer ownership to target */
|
|
txdw0 &= ~CP_RX_OWN;
|
|
|
|
/* reset error indicator bits */
|
|
txdw0 &= ~CP_TX_STATUS_UNF;
|
|
txdw0 &= ~CP_TX_STATUS_TES;
|
|
txdw0 &= ~CP_TX_STATUS_OWC;
|
|
txdw0 &= ~CP_TX_STATUS_LNKF;
|
|
txdw0 &= ~CP_TX_STATUS_EXC;
|
|
|
|
/* update ring data */
|
|
val = cpu_to_le32(txdw0);
|
|
cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
|
|
|
|
/* Now decide if descriptor being processed is holding the last segment of packet */
|
|
if (txdw0 & CP_TX_LS)
|
|
{
|
|
uint8_t dot1q_buffer_space[VLAN_HLEN];
|
|
uint16_t *dot1q_buffer;
|
|
|
|
DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
|
|
descriptor);
|
|
|
|
/* can transfer fully assembled packet */
|
|
|
|
uint8_t *saved_buffer = s->cplus_txbuffer;
|
|
int saved_size = s->cplus_txbuffer_offset;
|
|
int saved_buffer_len = s->cplus_txbuffer_len;
|
|
|
|
/* create vlan tag */
|
|
if (txdw1 & CP_TX_TAGC) {
|
|
/* the vlan tag is in BE byte order in the descriptor
|
|
* BE + le_to_cpu() + ~swap()~ = cpu */
|
|
DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
|
|
bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
|
|
|
|
dot1q_buffer = (uint16_t *) dot1q_buffer_space;
|
|
dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
|
|
/* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
|
|
dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
|
|
} else {
|
|
dot1q_buffer = NULL;
|
|
}
|
|
|
|
/* reset the card space to protect from recursive call */
|
|
s->cplus_txbuffer = NULL;
|
|
s->cplus_txbuffer_offset = 0;
|
|
s->cplus_txbuffer_len = 0;
|
|
|
|
if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
|
|
{
|
|
DPRINTF("+++ C+ mode offloaded task checksum\n");
|
|
|
|
/* ip packet header */
|
|
ip_header *ip = NULL;
|
|
int hlen = 0;
|
|
uint8_t ip_protocol = 0;
|
|
uint16_t ip_data_len = 0;
|
|
|
|
uint8_t *eth_payload_data = NULL;
|
|
size_t eth_payload_len = 0;
|
|
|
|
int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
|
|
if (proto == ETH_P_IP)
|
|
{
|
|
DPRINTF("+++ C+ mode has IP packet\n");
|
|
|
|
/* not aligned */
|
|
eth_payload_data = saved_buffer + ETH_HLEN;
|
|
eth_payload_len = saved_size - ETH_HLEN;
|
|
|
|
ip = (ip_header*)eth_payload_data;
|
|
|
|
if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
|
|
DPRINTF("+++ C+ mode packet has bad IP version %d "
|
|
"expected %d\n", IP_HEADER_VERSION(ip),
|
|
IP_HEADER_VERSION_4);
|
|
ip = NULL;
|
|
} else {
|
|
hlen = IP_HEADER_LENGTH(ip);
|
|
ip_protocol = ip->ip_p;
|
|
ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
|
|
}
|
|
}
|
|
|
|
if (ip)
|
|
{
|
|
if (txdw0 & CP_TX_IPCS)
|
|
{
|
|
DPRINTF("+++ C+ mode need IP checksum\n");
|
|
|
|
if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
|
|
/* bad packet header len */
|
|
/* or packet too short */
|
|
}
|
|
else
|
|
{
|
|
ip->ip_sum = 0;
|
|
ip->ip_sum = ip_checksum(ip, hlen);
|
|
DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
|
|
hlen, ip->ip_sum);
|
|
}
|
|
}
|
|
|
|
if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
|
|
{
|
|
int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
|
|
|
|
DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
|
|
"frame data %d specified MSS=%d\n", ETH_MTU,
|
|
ip_data_len, saved_size - ETH_HLEN, large_send_mss);
|
|
|
|
int tcp_send_offset = 0;
|
|
int send_count = 0;
|
|
|
|
/* maximum IP header length is 60 bytes */
|
|
uint8_t saved_ip_header[60];
|
|
|
|
/* save IP header template; data area is used in tcp checksum calculation */
|
|
memcpy(saved_ip_header, eth_payload_data, hlen);
|
|
|
|
/* a placeholder for checksum calculation routine in tcp case */
|
|
uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
|
// size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
|
|
|
/* pointer to TCP header */
|
|
tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
|
|
|
|
int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
|
|
|
|
/* ETH_MTU = ip header len + tcp header len + payload */
|
|
int tcp_data_len = ip_data_len - tcp_hlen;
|
|
int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
|
|
|
|
DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
|
|
"data len %d TCP chunk size %d\n", ip_data_len,
|
|
tcp_hlen, tcp_data_len, tcp_chunk_size);
|
|
|
|
/* note the cycle below overwrites IP header data,
|
|
but restores it from saved_ip_header before sending packet */
|
|
|
|
int is_last_frame = 0;
|
|
|
|
for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
|
|
{
|
|
uint16_t chunk_size = tcp_chunk_size;
|
|
|
|
/* check if this is the last frame */
|
|
if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
|
|
{
|
|
is_last_frame = 1;
|
|
chunk_size = tcp_data_len - tcp_send_offset;
|
|
}
|
|
|
|
DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
|
|
be32_to_cpu(p_tcp_hdr->th_seq));
|
|
|
|
/* add 4 TCP pseudoheader fields */
|
|
/* copy IP source and destination fields */
|
|
memcpy(data_to_checksum, saved_ip_header + 12, 8);
|
|
|
|
DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
|
|
"packet with %d bytes data\n", tcp_hlen +
|
|
chunk_size);
|
|
|
|
if (tcp_send_offset)
|
|
{
|
|
memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
|
|
}
|
|
|
|
/* keep PUSH and FIN flags only for the last frame */
|
|
if (!is_last_frame)
|
|
{
|
|
TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
|
|
}
|
|
|
|
/* recalculate TCP checksum */
|
|
ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
|
|
p_tcpip_hdr->zeros = 0;
|
|
p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
|
|
p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
|
|
|
|
p_tcp_hdr->th_sum = 0;
|
|
|
|
int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
|
|
DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
|
|
tcp_checksum);
|
|
|
|
p_tcp_hdr->th_sum = tcp_checksum;
|
|
|
|
/* restore IP header */
|
|
memcpy(eth_payload_data, saved_ip_header, hlen);
|
|
|
|
/* set IP data length and recalculate IP checksum */
|
|
ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
|
|
|
|
/* increment IP id for subsequent frames */
|
|
ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
|
|
|
|
ip->ip_sum = 0;
|
|
ip->ip_sum = ip_checksum(eth_payload_data, hlen);
|
|
DPRINTF("+++ C+ mode TSO IP header len=%d "
|
|
"checksum=%04x\n", hlen, ip->ip_sum);
|
|
|
|
int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
|
|
DPRINTF("+++ C+ mode TSO transferring packet size "
|
|
"%d\n", tso_send_size);
|
|
rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
|
|
0, (uint8_t *) dot1q_buffer);
|
|
|
|
/* add transferred count to TCP sequence number */
|
|
p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
|
|
++send_count;
|
|
}
|
|
|
|
/* Stop sending this frame */
|
|
saved_size = 0;
|
|
}
|
|
else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
|
|
{
|
|
DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
|
|
|
|
/* maximum IP header length is 60 bytes */
|
|
uint8_t saved_ip_header[60];
|
|
memcpy(saved_ip_header, eth_payload_data, hlen);
|
|
|
|
uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
|
|
// size_t data_to_checksum_len = eth_payload_len - hlen + 12;
|
|
|
|
/* add 4 TCP pseudoheader fields */
|
|
/* copy IP source and destination fields */
|
|
memcpy(data_to_checksum, saved_ip_header + 12, 8);
|
|
|
|
if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
|
|
{
|
|
DPRINTF("+++ C+ mode calculating TCP checksum for "
|
|
"packet with %d bytes data\n", ip_data_len);
|
|
|
|
ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
|
|
p_tcpip_hdr->zeros = 0;
|
|
p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
|
|
p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
|
|
|
|
tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
|
|
|
|
p_tcp_hdr->th_sum = 0;
|
|
|
|
int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
|
|
DPRINTF("+++ C+ mode TCP checksum %04x\n",
|
|
tcp_checksum);
|
|
|
|
p_tcp_hdr->th_sum = tcp_checksum;
|
|
}
|
|
else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
|
|
{
|
|
DPRINTF("+++ C+ mode calculating UDP checksum for "
|
|
"packet with %d bytes data\n", ip_data_len);
|
|
|
|
ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
|
|
p_udpip_hdr->zeros = 0;
|
|
p_udpip_hdr->ip_proto = IP_PROTO_UDP;
|
|
p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
|
|
|
|
udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
|
|
|
|
p_udp_hdr->uh_sum = 0;
|
|
|
|
int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
|
|
DPRINTF("+++ C+ mode UDP checksum %04x\n",
|
|
udp_checksum);
|
|
|
|
p_udp_hdr->uh_sum = udp_checksum;
|
|
}
|
|
|
|
/* restore IP header */
|
|
memcpy(eth_payload_data, saved_ip_header, hlen);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* update tally counter */
|
|
++s->tally_counters.TxOk;
|
|
|
|
DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
|
|
|
|
rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
|
|
(uint8_t *) dot1q_buffer);
|
|
|
|
/* restore card space if there was no recursion and reset offset */
|
|
if (!s->cplus_txbuffer)
|
|
{
|
|
s->cplus_txbuffer = saved_buffer;
|
|
s->cplus_txbuffer_len = saved_buffer_len;
|
|
s->cplus_txbuffer_offset = 0;
|
|
}
|
|
else
|
|
{
|
|
g_free(saved_buffer);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void rtl8139_cplus_transmit(RTL8139State *s)
|
|
{
|
|
int txcount = 0;
|
|
|
|
while (rtl8139_cplus_transmit_one(s))
|
|
{
|
|
++txcount;
|
|
}
|
|
|
|
/* Mark transfer completed */
|
|
if (!txcount)
|
|
{
|
|
DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
|
|
s->currCPlusTxDesc);
|
|
}
|
|
else
|
|
{
|
|
/* update interrupt status */
|
|
s->IntrStatus |= TxOK;
|
|
rtl8139_update_irq(s);
|
|
}
|
|
}
|
|
|
|
static void rtl8139_transmit(RTL8139State *s)
|
|
{
|
|
int descriptor = s->currTxDesc, txcount = 0;
|
|
|
|
/*while*/
|
|
if (rtl8139_transmit_one(s, descriptor))
|
|
{
|
|
++s->currTxDesc;
|
|
s->currTxDesc %= 4;
|
|
++txcount;
|
|
}
|
|
|
|
/* Mark transfer completed */
|
|
if (!txcount)
|
|
{
|
|
DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
|
|
s->currTxDesc);
|
|
}
|
|
}
|
|
|
|
static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
|
|
{
|
|
|
|
int descriptor = txRegOffset/4;
|
|
|
|
/* handle C+ transmit mode register configuration */
|
|
|
|
if (s->cplus_enabled)
|
|
{
|
|
DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
|
|
"descriptor=%d\n", txRegOffset, val, descriptor);
|
|
|
|
/* handle Dump Tally Counters command */
|
|
s->TxStatus[descriptor] = val;
|
|
|
|
if (descriptor == 0 && (val & 0x8))
|
|
{
|
|
target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
|
|
|
|
/* dump tally counters to specified memory location */
|
|
RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
|
|
|
|
/* mark dump completed */
|
|
s->TxStatus[0] &= ~0x8;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
|
|
txRegOffset, val, descriptor);
|
|
|
|
/* mask only reserved bits */
|
|
val &= ~0xff00c000; /* these bits are reset on write */
|
|
val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
|
|
|
|
s->TxStatus[descriptor] = val;
|
|
|
|
/* attempt to start transmission */
|
|
rtl8139_transmit(s);
|
|
}
|
|
|
|
static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
|
|
{
|
|
uint32_t ret = s->TxStatus[txRegOffset/4];
|
|
|
|
DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint16_t rtl8139_TSAD_read(RTL8139State *s)
|
|
{
|
|
uint16_t ret = 0;
|
|
|
|
/* Simulate TSAD, it is read only anyway */
|
|
|
|
ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
|
|
|((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
|
|
|((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
|
|
|((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
|
|
|
|
|((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
|
|
|((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
|
|
|((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
|
|
|((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
|
|
|
|
|((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
|
|
|((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
|
|
|((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
|
|
|((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
|
|
|
|
|((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
|
|
|((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
|
|
|((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
|
|
|((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
|
|
|
|
|
|
DPRINTF("TSAD read val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint16_t rtl8139_CSCR_read(RTL8139State *s)
|
|
{
|
|
uint16_t ret = s->CSCR;
|
|
|
|
DPRINTF("CSCR read val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
|
|
{
|
|
DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
|
|
|
|
s->TxAddr[txAddrOffset/4] = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
|
|
{
|
|
uint32_t ret = s->TxAddr[txAddrOffset/4];
|
|
|
|
DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
DPRINTF("RxBufPtr write val=0x%04x\n", val);
|
|
|
|
/* this value is off by 16 */
|
|
s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
|
|
|
|
DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
|
|
s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
|
|
}
|
|
|
|
static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
|
|
{
|
|
/* this value is off by 16 */
|
|
uint32_t ret = s->RxBufPtr - 0x10;
|
|
|
|
DPRINTF("RxBufPtr read val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
|
|
{
|
|
/* this value is NOT off by 16 */
|
|
uint32_t ret = s->RxBufAddr;
|
|
|
|
DPRINTF("RxBufAddr read val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
DPRINTF("RxBuf write val=0x%08x\n", val);
|
|
|
|
s->RxBuf = val;
|
|
|
|
/* may need to reset rxring here */
|
|
}
|
|
|
|
static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->RxBuf;
|
|
|
|
DPRINTF("RxBuf read val=0x%08x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
DPRINTF("IntrMask write(w) val=0x%04x\n", val);
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0x1e00, s->IntrMask);
|
|
|
|
s->IntrMask = val;
|
|
|
|
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
rtl8139_update_irq(s);
|
|
|
|
}
|
|
|
|
static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->IntrMask;
|
|
|
|
DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
|
|
|
|
#if 0
|
|
|
|
/* writing to ISR has no effect */
|
|
|
|
return;
|
|
|
|
#else
|
|
uint16_t newStatus = s->IntrStatus & ~val;
|
|
|
|
/* mask unwritable bits */
|
|
newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
|
|
|
|
/* writing 1 to interrupt status register bit clears it */
|
|
s->IntrStatus = 0;
|
|
rtl8139_update_irq(s);
|
|
|
|
s->IntrStatus = newStatus;
|
|
/*
|
|
* Computing if we miss an interrupt here is not that correct but
|
|
* considered that we should have had already an interrupt
|
|
* and probably emulated is slower is better to assume this resetting was
|
|
* done before testing on previous rtl8139_update_irq lead to IRQ loosing
|
|
*/
|
|
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
rtl8139_update_irq(s);
|
|
|
|
#endif
|
|
}
|
|
|
|
static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
|
|
{
|
|
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
|
|
uint32_t ret = s->IntrStatus;
|
|
|
|
DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
|
|
|
|
#if 0
|
|
|
|
/* reading ISR clears all interrupts */
|
|
s->IntrStatus = 0;
|
|
|
|
rtl8139_update_irq(s);
|
|
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
|
|
{
|
|
DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
|
|
|
|
/* mask unwritable bits */
|
|
val = SET_MASKED(val, 0xf000, s->MultiIntr);
|
|
|
|
s->MultiIntr = val;
|
|
}
|
|
|
|
static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
|
|
{
|
|
uint32_t ret = s->MultiIntr;
|
|
|
|
DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
|
|
{
|
|
RTL8139State *s = opaque;
|
|
|
|
addr &= 0xff;
|
|
|
|
switch (addr)
|
|
{
|
|
case MAC0 ... MAC0+5:
|
|
s->phys[addr - MAC0] = val;
|
|
break;
|
|
case MAC0+6 ... MAC0+7:
|
|
/* reserved */
|
|
break;
|
|
case MAR0 ... MAR0+7:
|
|
s->mult[addr - MAR0] = val;
|
|
break;
|
|
case ChipCmd:
|
|
rtl8139_ChipCmd_write(s, val);
|
|
break;
|
|
case Cfg9346:
|
|
rtl8139_Cfg9346_write(s, val);
|
|
break;
|
|
case TxConfig: /* windows driver sometimes writes using byte-lenth call */
|
|
rtl8139_TxConfig_writeb(s, val);
|
|
break;
|
|
case Config0:
|
|
rtl8139_Config0_write(s, val);
|
|
break;
|
|
case Config1:
|
|
rtl8139_Config1_write(s, val);
|
|
break;
|
|
case Config3:
|
|
rtl8139_Config3_write(s, val);
|
|
break;
|
|
case Config4:
|
|
rtl8139_Config4_write(s, val);
|
|
break;
|
|
case Config5:
|
|
rtl8139_Config5_write(s, val);
|
|
break;
|
|
case MediaStatus:
|
|
/* ignore */
|
|
DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
|
|
val);
|
|
break;
|
|
|
|
case HltClk:
|
|
DPRINTF("HltClk write val=0x%08x\n", val);
|
|
if (val == 'R')
|
|
{
|
|
s->clock_enabled = 1;
|
|
}
|
|
else if (val == 'H')
|
|
{
|
|
s->clock_enabled = 0;
|
|
}
|
|
break;
|
|
|
|
case TxThresh:
|
|
DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
|
|
s->TxThresh = val;
|
|
break;
|
|
|
|
case TxPoll:
|
|
DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
|
|
if (val & (1 << 7))
|
|
{
|
|
DPRINTF("C+ TxPoll high priority transmission (not "
|
|
"implemented)\n");
|
|
//rtl8139_cplus_transmit(s);
|
|
}
|
|
if (val & (1 << 6))
|
|
{
|
|
DPRINTF("C+ TxPoll normal priority transmission\n");
|
|
rtl8139_cplus_transmit(s);
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
|
|
val);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
|
|
{
|
|
RTL8139State *s = opaque;
|
|
|
|
addr &= 0xfe;
|
|
|
|
switch (addr)
|
|
{
|
|
case IntrMask:
|
|
rtl8139_IntrMask_write(s, val);
|
|
break;
|
|
|
|
case IntrStatus:
|
|
rtl8139_IntrStatus_write(s, val);
|
|
break;
|
|
|
|
case MultiIntr:
|
|
rtl8139_MultiIntr_write(s, val);
|
|
break;
|
|
|
|
case RxBufPtr:
|
|
rtl8139_RxBufPtr_write(s, val);
|
|
break;
|
|
|
|
case BasicModeCtrl:
|
|
rtl8139_BasicModeCtrl_write(s, val);
|
|
break;
|
|
case BasicModeStatus:
|
|
rtl8139_BasicModeStatus_write(s, val);
|
|
break;
|
|
case NWayAdvert:
|
|
DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
|
|
s->NWayAdvert = val;
|
|
break;
|
|
case NWayLPAR:
|
|
DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
|
|
break;
|
|
case NWayExpansion:
|
|
DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
|
|
s->NWayExpansion = val;
|
|
break;
|
|
|
|
case CpCmd:
|
|
rtl8139_CpCmd_write(s, val);
|
|
break;
|
|
|
|
case IntrMitigate:
|
|
rtl8139_IntrMitigate_write(s, val);
|
|
break;
|
|
|
|
default:
|
|
DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
|
|
addr, val);
|
|
|
|
rtl8139_io_writeb(opaque, addr, val & 0xff);
|
|
rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
|
|
{
|
|
int64_t pci_time, next_time;
|
|
uint32_t low_pci;
|
|
|
|
DPRINTF("entered rtl8139_set_next_tctr_time\n");
|
|
|
|
if (s->TimerExpire && current_time >= s->TimerExpire) {
|
|
s->IntrStatus |= PCSTimeout;
|
|
rtl8139_update_irq(s);
|
|
}
|
|
|
|
/* Set QEMU timer only if needed that is
|
|
* - TimerInt <> 0 (we have a timer)
|
|
* - mask = 1 (we want an interrupt timer)
|
|
* - irq = 0 (irq is not already active)
|
|
* If any of above change we need to compute timer again
|
|
* Also we must check if timer is passed without QEMU timer
|
|
*/
|
|
s->TimerExpire = 0;
|
|
if (!s->TimerInt) {
|
|
return;
|
|
}
|
|
|
|
pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
|
|
get_ticks_per_sec());
|
|
low_pci = pci_time & 0xffffffff;
|
|
pci_time = pci_time - low_pci + s->TimerInt;
|
|
if (low_pci >= s->TimerInt) {
|
|
pci_time += 0x100000000LL;
|
|
}
|
|
next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
|
|
PCI_FREQUENCY);
|
|
s->TimerExpire = next_time;
|
|
|
|
if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
|
|
qemu_mod_timer(s->timer, next_time);
|
|
}
|
|
}
|
|
|
|
static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
|
|
{
|
|
RTL8139State *s = opaque;
|
|
|
|
addr &= 0xfc;
|
|
|
|
switch (addr)
|
|
{
|
|
case RxMissed:
|
|
DPRINTF("RxMissed clearing on write\n");
|
|
s->RxMissed = 0;
|
|
break;
|
|
|
|
case TxConfig:
|
|
rtl8139_TxConfig_write(s, val);
|
|
break;
|
|
|
|
case RxConfig:
|
|
rtl8139_RxConfig_write(s, val);
|
|
break;
|
|
|
|
case TxStatus0 ... TxStatus0+4*4-1:
|
|
rtl8139_TxStatus_write(s, addr-TxStatus0, val);
|
|
break;
|
|
|
|
case TxAddr0 ... TxAddr0+4*4-1:
|
|
rtl8139_TxAddr_write(s, addr-TxAddr0, val);
|
|
break;
|
|
|
|
case RxBuf:
|
|
rtl8139_RxBuf_write(s, val);
|
|
break;
|
|
|
|
case RxRingAddrLO:
|
|
DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
|
|
s->RxRingAddrLO = val;
|
|
break;
|
|
|
|
case RxRingAddrHI:
|
|
DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
|
|
s->RxRingAddrHI = val;
|
|
break;
|
|
|
|
case Timer:
|
|
DPRINTF("TCTR Timer reset on write\n");
|
|
s->TCTR_base = qemu_get_clock_ns(vm_clock);
|
|
rtl8139_set_next_tctr_time(s, s->TCTR_base);
|
|
break;
|
|
|
|
case FlashReg:
|
|
DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
|
|
if (s->TimerInt != val) {
|
|
s->TimerInt = val;
|
|
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
}
|
|
break;
|
|
|
|
default:
|
|
DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
|
|
addr, val);
|
|
rtl8139_io_writeb(opaque, addr, val & 0xff);
|
|
rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
|
|
rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
|
|
rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
|
|
{
|
|
RTL8139State *s = opaque;
|
|
int ret;
|
|
|
|
addr &= 0xff;
|
|
|
|
switch (addr)
|
|
{
|
|
case MAC0 ... MAC0+5:
|
|
ret = s->phys[addr - MAC0];
|
|
break;
|
|
case MAC0+6 ... MAC0+7:
|
|
ret = 0;
|
|
break;
|
|
case MAR0 ... MAR0+7:
|
|
ret = s->mult[addr - MAR0];
|
|
break;
|
|
case ChipCmd:
|
|
ret = rtl8139_ChipCmd_read(s);
|
|
break;
|
|
case Cfg9346:
|
|
ret = rtl8139_Cfg9346_read(s);
|
|
break;
|
|
case Config0:
|
|
ret = rtl8139_Config0_read(s);
|
|
break;
|
|
case Config1:
|
|
ret = rtl8139_Config1_read(s);
|
|
break;
|
|
case Config3:
|
|
ret = rtl8139_Config3_read(s);
|
|
break;
|
|
case Config4:
|
|
ret = rtl8139_Config4_read(s);
|
|
break;
|
|
case Config5:
|
|
ret = rtl8139_Config5_read(s);
|
|
break;
|
|
|
|
case MediaStatus:
|
|
ret = 0xd0;
|
|
DPRINTF("MediaStatus read 0x%x\n", ret);
|
|
break;
|
|
|
|
case HltClk:
|
|
ret = s->clock_enabled;
|
|
DPRINTF("HltClk read 0x%x\n", ret);
|
|
break;
|
|
|
|
case PCIRevisionID:
|
|
ret = RTL8139_PCI_REVID;
|
|
DPRINTF("PCI Revision ID read 0x%x\n", ret);
|
|
break;
|
|
|
|
case TxThresh:
|
|
ret = s->TxThresh;
|
|
DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
|
|
break;
|
|
|
|
case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
|
|
ret = s->TxConfig >> 24;
|
|
DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
|
|
break;
|
|
|
|
default:
|
|
DPRINTF("not implemented read(b) addr=0x%x\n", addr);
|
|
ret = 0;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
|
|
{
|
|
RTL8139State *s = opaque;
|
|
uint32_t ret;
|
|
|
|
addr &= 0xfe; /* mask lower bit */
|
|
|
|
switch (addr)
|
|
{
|
|
case IntrMask:
|
|
ret = rtl8139_IntrMask_read(s);
|
|
break;
|
|
|
|
case IntrStatus:
|
|
ret = rtl8139_IntrStatus_read(s);
|
|
break;
|
|
|
|
case MultiIntr:
|
|
ret = rtl8139_MultiIntr_read(s);
|
|
break;
|
|
|
|
case RxBufPtr:
|
|
ret = rtl8139_RxBufPtr_read(s);
|
|
break;
|
|
|
|
case RxBufAddr:
|
|
ret = rtl8139_RxBufAddr_read(s);
|
|
break;
|
|
|
|
case BasicModeCtrl:
|
|
ret = rtl8139_BasicModeCtrl_read(s);
|
|
break;
|
|
case BasicModeStatus:
|
|
ret = rtl8139_BasicModeStatus_read(s);
|
|
break;
|
|
case NWayAdvert:
|
|
ret = s->NWayAdvert;
|
|
DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
|
|
break;
|
|
case NWayLPAR:
|
|
ret = s->NWayLPAR;
|
|
DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
|
|
break;
|
|
case NWayExpansion:
|
|
ret = s->NWayExpansion;
|
|
DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
|
|
break;
|
|
|
|
case CpCmd:
|
|
ret = rtl8139_CpCmd_read(s);
|
|
break;
|
|
|
|
case IntrMitigate:
|
|
ret = rtl8139_IntrMitigate_read(s);
|
|
break;
|
|
|
|
case TxSummary:
|
|
ret = rtl8139_TSAD_read(s);
|
|
break;
|
|
|
|
case CSCR:
|
|
ret = rtl8139_CSCR_read(s);
|
|
break;
|
|
|
|
default:
|
|
DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
|
|
|
|
ret = rtl8139_io_readb(opaque, addr);
|
|
ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
|
|
|
|
DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
|
|
{
|
|
RTL8139State *s = opaque;
|
|
uint32_t ret;
|
|
|
|
addr &= 0xfc; /* also mask low 2 bits */
|
|
|
|
switch (addr)
|
|
{
|
|
case RxMissed:
|
|
ret = s->RxMissed;
|
|
|
|
DPRINTF("RxMissed read val=0x%08x\n", ret);
|
|
break;
|
|
|
|
case TxConfig:
|
|
ret = rtl8139_TxConfig_read(s);
|
|
break;
|
|
|
|
case RxConfig:
|
|
ret = rtl8139_RxConfig_read(s);
|
|
break;
|
|
|
|
case TxStatus0 ... TxStatus0+4*4-1:
|
|
ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
|
|
break;
|
|
|
|
case TxAddr0 ... TxAddr0+4*4-1:
|
|
ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
|
|
break;
|
|
|
|
case RxBuf:
|
|
ret = rtl8139_RxBuf_read(s);
|
|
break;
|
|
|
|
case RxRingAddrLO:
|
|
ret = s->RxRingAddrLO;
|
|
DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
|
|
break;
|
|
|
|
case RxRingAddrHI:
|
|
ret = s->RxRingAddrHI;
|
|
DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
|
|
break;
|
|
|
|
case Timer:
|
|
ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
|
|
PCI_FREQUENCY, get_ticks_per_sec());
|
|
DPRINTF("TCTR Timer read val=0x%08x\n", ret);
|
|
break;
|
|
|
|
case FlashReg:
|
|
ret = s->TimerInt;
|
|
DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
|
|
break;
|
|
|
|
default:
|
|
DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
|
|
|
|
ret = rtl8139_io_readb(opaque, addr);
|
|
ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
|
|
ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
|
|
ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
|
|
|
|
DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* */
|
|
|
|
static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
|
}
|
|
|
|
static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
rtl8139_io_writew(opaque, addr & 0xFF, val);
|
|
}
|
|
|
|
static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
rtl8139_io_writel(opaque, addr & 0xFF, val);
|
|
}
|
|
|
|
static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
|
|
{
|
|
return rtl8139_io_readb(opaque, addr & 0xFF);
|
|
}
|
|
|
|
static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
|
|
{
|
|
return rtl8139_io_readw(opaque, addr & 0xFF);
|
|
}
|
|
|
|
static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
|
|
{
|
|
return rtl8139_io_readl(opaque, addr & 0xFF);
|
|
}
|
|
|
|
/* */
|
|
|
|
static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
rtl8139_io_writeb(opaque, addr & 0xFF, val);
|
|
}
|
|
|
|
static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
rtl8139_io_writew(opaque, addr & 0xFF, val);
|
|
}
|
|
|
|
static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
rtl8139_io_writel(opaque, addr & 0xFF, val);
|
|
}
|
|
|
|
static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
return rtl8139_io_readb(opaque, addr & 0xFF);
|
|
}
|
|
|
|
static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
|
|
return val;
|
|
}
|
|
|
|
static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
|
|
return val;
|
|
}
|
|
|
|
static int rtl8139_post_load(void *opaque, int version_id)
|
|
{
|
|
RTL8139State* s = opaque;
|
|
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
if (version_id < 4) {
|
|
s->cplus_enabled = s->CpCmd != 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool rtl8139_hotplug_ready_needed(void *opaque)
|
|
{
|
|
return qdev_machine_modified();
|
|
}
|
|
|
|
static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
|
|
.name = "rtl8139/hotplug_ready",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void rtl8139_pre_save(void *opaque)
|
|
{
|
|
RTL8139State* s = opaque;
|
|
int64_t current_time = qemu_get_clock_ns(vm_clock);
|
|
|
|
/* set IntrStatus correctly */
|
|
rtl8139_set_next_tctr_time(s, current_time);
|
|
s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
|
|
get_ticks_per_sec());
|
|
s->rtl8139_mmio_io_addr_dummy = 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_rtl8139 = {
|
|
.name = "rtl8139",
|
|
.version_id = 4,
|
|
.minimum_version_id = 3,
|
|
.minimum_version_id_old = 3,
|
|
.post_load = rtl8139_post_load,
|
|
.pre_save = rtl8139_pre_save,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_PCI_DEVICE(dev, RTL8139State),
|
|
VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
|
|
VMSTATE_BUFFER(mult, RTL8139State),
|
|
VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
|
|
VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
|
|
|
|
VMSTATE_UINT32(RxBuf, RTL8139State),
|
|
VMSTATE_UINT32(RxBufferSize, RTL8139State),
|
|
VMSTATE_UINT32(RxBufPtr, RTL8139State),
|
|
VMSTATE_UINT32(RxBufAddr, RTL8139State),
|
|
|
|
VMSTATE_UINT16(IntrStatus, RTL8139State),
|
|
VMSTATE_UINT16(IntrMask, RTL8139State),
|
|
|
|
VMSTATE_UINT32(TxConfig, RTL8139State),
|
|
VMSTATE_UINT32(RxConfig, RTL8139State),
|
|
VMSTATE_UINT32(RxMissed, RTL8139State),
|
|
VMSTATE_UINT16(CSCR, RTL8139State),
|
|
|
|
VMSTATE_UINT8(Cfg9346, RTL8139State),
|
|
VMSTATE_UINT8(Config0, RTL8139State),
|
|
VMSTATE_UINT8(Config1, RTL8139State),
|
|
VMSTATE_UINT8(Config3, RTL8139State),
|
|
VMSTATE_UINT8(Config4, RTL8139State),
|
|
VMSTATE_UINT8(Config5, RTL8139State),
|
|
|
|
VMSTATE_UINT8(clock_enabled, RTL8139State),
|
|
VMSTATE_UINT8(bChipCmdState, RTL8139State),
|
|
|
|
VMSTATE_UINT16(MultiIntr, RTL8139State),
|
|
|
|
VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
|
|
VMSTATE_UINT16(BasicModeStatus, RTL8139State),
|
|
VMSTATE_UINT16(NWayAdvert, RTL8139State),
|
|
VMSTATE_UINT16(NWayLPAR, RTL8139State),
|
|
VMSTATE_UINT16(NWayExpansion, RTL8139State),
|
|
|
|
VMSTATE_UINT16(CpCmd, RTL8139State),
|
|
VMSTATE_UINT8(TxThresh, RTL8139State),
|
|
|
|
VMSTATE_UNUSED(4),
|
|
VMSTATE_MACADDR(conf.macaddr, RTL8139State),
|
|
VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
|
|
|
|
VMSTATE_UINT32(currTxDesc, RTL8139State),
|
|
VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
|
|
VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
|
|
VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
|
|
VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
|
|
|
|
VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
|
|
VMSTATE_INT32(eeprom.mode, RTL8139State),
|
|
VMSTATE_UINT32(eeprom.tick, RTL8139State),
|
|
VMSTATE_UINT8(eeprom.address, RTL8139State),
|
|
VMSTATE_UINT16(eeprom.input, RTL8139State),
|
|
VMSTATE_UINT16(eeprom.output, RTL8139State),
|
|
|
|
VMSTATE_UINT8(eeprom.eecs, RTL8139State),
|
|
VMSTATE_UINT8(eeprom.eesk, RTL8139State),
|
|
VMSTATE_UINT8(eeprom.eedi, RTL8139State),
|
|
VMSTATE_UINT8(eeprom.eedo, RTL8139State),
|
|
|
|
VMSTATE_UINT32(TCTR, RTL8139State),
|
|
VMSTATE_UINT32(TimerInt, RTL8139State),
|
|
VMSTATE_INT64(TCTR_base, RTL8139State),
|
|
|
|
VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
|
|
vmstate_tally_counters, RTL8139TallyCounters),
|
|
|
|
VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
.subsections = (VMStateSubsection []) {
|
|
{
|
|
.vmsd = &vmstate_rtl8139_hotplug_ready,
|
|
.needed = rtl8139_hotplug_ready_needed,
|
|
}, {
|
|
/* empty */
|
|
}
|
|
}
|
|
};
|
|
|
|
/***********************************************************/
|
|
/* PCI RTL8139 definitions */
|
|
|
|
static const MemoryRegionPortio rtl8139_portio[] = {
|
|
{ 0, 0x100, 1, .read = rtl8139_ioport_readb, },
|
|
{ 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
|
|
{ 0, 0x100, 2, .read = rtl8139_ioport_readw, },
|
|
{ 0, 0x100, 2, .write = rtl8139_ioport_writew, },
|
|
{ 0, 0x100, 4, .read = rtl8139_ioport_readl, },
|
|
{ 0, 0x100, 4, .write = rtl8139_ioport_writel, },
|
|
PORTIO_END_OF_LIST()
|
|
};
|
|
|
|
static const MemoryRegionOps rtl8139_io_ops = {
|
|
.old_portio = rtl8139_portio,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
static const MemoryRegionOps rtl8139_mmio_ops = {
|
|
.old_mmio = {
|
|
.read = {
|
|
rtl8139_mmio_readb,
|
|
rtl8139_mmio_readw,
|
|
rtl8139_mmio_readl,
|
|
},
|
|
.write = {
|
|
rtl8139_mmio_writeb,
|
|
rtl8139_mmio_writew,
|
|
rtl8139_mmio_writel,
|
|
},
|
|
},
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
static void rtl8139_timer(void *opaque)
|
|
{
|
|
RTL8139State *s = opaque;
|
|
|
|
if (!s->clock_enabled)
|
|
{
|
|
DPRINTF(">>> timer: clock is not running\n");
|
|
return;
|
|
}
|
|
|
|
s->IntrStatus |= PCSTimeout;
|
|
rtl8139_update_irq(s);
|
|
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
}
|
|
|
|
static void rtl8139_cleanup(VLANClientState *nc)
|
|
{
|
|
RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
|
|
|
s->nic = NULL;
|
|
}
|
|
|
|
static int pci_rtl8139_uninit(PCIDevice *dev)
|
|
{
|
|
RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
|
|
|
|
memory_region_destroy(&s->bar_io);
|
|
memory_region_destroy(&s->bar_mem);
|
|
if (s->cplus_txbuffer) {
|
|
g_free(s->cplus_txbuffer);
|
|
s->cplus_txbuffer = NULL;
|
|
}
|
|
qemu_del_timer(s->timer);
|
|
qemu_free_timer(s->timer);
|
|
qemu_del_vlan_client(&s->nic->nc);
|
|
return 0;
|
|
}
|
|
|
|
static NetClientInfo net_rtl8139_info = {
|
|
.type = NET_CLIENT_TYPE_NIC,
|
|
.size = sizeof(NICState),
|
|
.can_receive = rtl8139_can_receive,
|
|
.receive = rtl8139_receive,
|
|
.cleanup = rtl8139_cleanup,
|
|
};
|
|
|
|
static int pci_rtl8139_init(PCIDevice *dev)
|
|
{
|
|
RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
|
|
uint8_t *pci_conf;
|
|
|
|
pci_conf = s->dev.config;
|
|
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
|
|
/* TODO: start of capability list, but no capability
|
|
* list bit in status register, and offset 0xdc seems unused. */
|
|
pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
|
|
|
|
memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
|
|
memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
|
|
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
|
|
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
|
|
|
|
qemu_macaddr_default_if_unset(&s->conf.macaddr);
|
|
|
|
/* prepare eeprom */
|
|
s->eeprom.contents[0] = 0x8129;
|
|
#if 1
|
|
/* PCI vendor and device ID should be mirrored here */
|
|
s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
|
|
s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
|
|
#endif
|
|
s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
|
|
s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
|
|
s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
|
|
|
|
s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
|
|
dev->qdev.info->name, dev->qdev.id, s);
|
|
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
|
|
|
|
s->cplus_txbuffer = NULL;
|
|
s->cplus_txbuffer_len = 0;
|
|
s->cplus_txbuffer_offset = 0;
|
|
|
|
s->TimerExpire = 0;
|
|
s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
|
|
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
|
|
|
|
add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static PCIDeviceInfo rtl8139_info = {
|
|
.qdev.name = "rtl8139",
|
|
.qdev.size = sizeof(RTL8139State),
|
|
.qdev.reset = rtl8139_reset,
|
|
.qdev.vmsd = &vmstate_rtl8139,
|
|
.init = pci_rtl8139_init,
|
|
.exit = pci_rtl8139_uninit,
|
|
.romfile = "pxe-rtl8139.rom",
|
|
.vendor_id = PCI_VENDOR_ID_REALTEK,
|
|
.device_id = PCI_DEVICE_ID_REALTEK_8139,
|
|
.revision = RTL8139_PCI_REVID, /* >=0x20 is for 8139C+ */
|
|
.class_id = PCI_CLASS_NETWORK_ETHERNET,
|
|
.qdev.props = (Property[]) {
|
|
DEFINE_NIC_PROPERTIES(RTL8139State, conf),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
}
|
|
};
|
|
|
|
static void rtl8139_register_devices(void)
|
|
{
|
|
pci_qdev_register(&rtl8139_info);
|
|
}
|
|
|
|
device_init(rtl8139_register_devices)
|