f18c697b55
Now, AER capa version is fixed to v2, if assigned device isn't v2, then this value will be inconsistent between guest and host Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com> Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
108 lines
3.5 KiB
C
108 lines
3.5 KiB
C
/*
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* pcie_aer.h
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_PCIE_AER_H
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#define QEMU_PCIE_AER_H
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#include "hw/hw.h"
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/* definitions which PCIExpressDevice uses */
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/* AER log */
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struct PCIEAERLog {
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/* This structure is saved/loaded.
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So explicitly size them instead of unsigned int */
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/* the number of currently recorded log in log member */
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uint16_t log_num;
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/*
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* The maximum number of the log. Errors can be logged up to this.
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*
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* This is configurable property.
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* The specified value will be clipped down to PCIE_AER_LOG_MAX_LIMIT
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* to avoid unreasonable memory usage.
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* I bet that 128 log size would be big enough, otherwise too many errors
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* for system to function normaly. But could consecutive errors occur?
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*/
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#define PCIE_AER_LOG_MAX_DEFAULT 8
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#define PCIE_AER_LOG_MAX_LIMIT 128
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uint16_t log_max;
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/* Error log. log_max-sized array */
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PCIEAERErr *log;
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};
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/* aer error message: error signaling message has only error severity and
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source id. See 2.2.8.3 error signaling messages */
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struct PCIEAERMsg {
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/*
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* PCI_ERR_ROOT_CMD_{COR, NONFATAL, FATAL}_EN
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* = PCI_EXP_DEVCTL_{CERE, NFERE, FERE}
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*/
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uint32_t severity;
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uint16_t source_id; /* bdf */
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};
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static inline bool
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pcie_aer_msg_is_uncor(const PCIEAERMsg *msg)
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{
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return msg->severity == PCI_ERR_ROOT_CMD_NONFATAL_EN ||
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msg->severity == PCI_ERR_ROOT_CMD_FATAL_EN;
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}
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/* error */
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struct PCIEAERErr {
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uint32_t status; /* error status bits */
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uint16_t source_id; /* bdf */
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#define PCIE_AER_ERR_IS_CORRECTABLE 0x1 /* correctable/uncorrectable */
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#define PCIE_AER_ERR_MAYBE_ADVISORY 0x2 /* maybe advisory non-fatal */
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#define PCIE_AER_ERR_HEADER_VALID 0x4 /* TLP header is logged */
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#define PCIE_AER_ERR_TLP_PREFIX_PRESENT 0x8 /* TLP Prefix is logged */
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uint16_t flags;
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uint32_t header[4]; /* TLP header */
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uint32_t prefix[4]; /* TLP header prefix */
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};
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extern const VMStateDescription vmstate_pcie_aer_log;
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int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
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uint16_t size, Error **errp);
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void pcie_aer_exit(PCIDevice *dev);
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void pcie_aer_write_config(PCIDevice *dev,
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uint32_t addr, uint32_t val, int len);
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/* aer root port */
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void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector);
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void pcie_aer_root_init(PCIDevice *dev);
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void pcie_aer_root_reset(PCIDevice *dev);
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void pcie_aer_root_write_config(PCIDevice *dev,
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uint32_t addr, uint32_t val, int len,
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uint32_t root_cmd_prev);
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/* error injection */
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int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err);
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void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg);
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#endif /* QEMU_PCIE_AER_H */
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