Peter Maydell
deee6ff7b7
Fixes for TLB_BSWAP
Coversion of NOTDIRTY and ROM handling to cputlb
Followup cleanups to cputlb
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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190925' into staging
Fixes for TLB_BSWAP
Coversion of NOTDIRTY and ROM handling to cputlb
Followup cleanups to cputlb
# gpg: Signature made Wed 25 Sep 2019 19:41:17 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20190925:
cputlb: Pass retaddr to tb_check_watchpoint
cputlb: Pass retaddr to tb_invalidate_phys_page_fast
cputlb: Remove tb_invalidate_phys_page_range is_cpu_write_access
cputlb: Remove cpu->mem_io_vaddr
cputlb: Handle TLB_NOTDIRTY in probe_access
cputlb: Merge and move memory_notdirty_write_{prepare,complete}
cputlb: Partially inline memory_region_section_get_iotlb
cputlb: Move NOTDIRTY handling from I/O path to TLB path
cputlb: Move ROM handling from I/O path to TLB path
exec: Adjust notdirty tracing
cputlb: Introduce TLB_BSWAP
cputlb: Split out load/store_memop
cputlb: Use qemu_build_not_reached in load/store_helpers
qemu/compiler.h: Add qemu_build_not_reached
cputlb: Disable __always_inline__ without optimization
exec: Use TARGET_PAGE_BITS_MIN for TLB flags
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>