Zhuang, Siwei (Data61, Kensington NSW) 6478dd745d hw/riscv: Add optional symbol callback ptr to riscv_load_kernel() ... This patch adds an optional function pointer, "sym_cb", to riscv_load_kernel() which provides the possibility to access the symbol table during kernel loading. The pointer is ignored, if supplied with Image or uImage file. The Spike board requires the access to locate the HTIF symbols. Fixes: 0ac24d56c5 ("hw/riscv: Split out the boot functions") Buglink: https://bugs.launchpad.net/qemu/+bug/1835827 Signed-off-by: Siwei Zhuang <siwei.zhuang@data61.csiro.au> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2019-11-25 12:34:52 -08:00
..
boot.h	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	2019-11-25 12:34:52 -08:00
riscv_hart.h	riscv: hart: Add a "hartid-base" property to RISC-V hart array	2019-09-17 08:42:47 -07:00
riscv_htif.h
sifive_clint.h
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e_prci.h	riscv: sifive_e: prci: Update the PRCI register block size	2019-09-17 08:42:46 -07:00
sifive_e.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_gpio.h
sifive_plic.h	riscv: plic: Remove unused interrupt functions	2019-09-17 08:42:42 -07:00
sifive_test.h	riscv: sifive_test: Add reset functionality	2019-09-17 08:42:44 -07:00
sifive_u_otp.h	riscv: sifive: Implement a model for SiFive FU540 OTP	2019-09-17 08:42:49 -07:00
sifive_u_prci.h	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	2019-09-17 08:42:48 -07:00
sifive_u.h	riscv/sifive_u: Add the start-in-flash property	2019-10-28 07:47:28 -07:00
sifive_uart.h
spike.h	riscv: hw: Drop "clock-frequency" property of cpu nodes	2019-10-28 07:47:27 -07:00
virt.h	riscv/virt: Add the PFlash CFI01 device	2019-10-28 07:47:28 -07:00