Eduardo Habkost 9ab2237f19 i386: Add new versions of Skylake/Cascadelake/Icelake without TSX ... One of the mitigation methods for TAA[1] is to disable TSX support on the host system. Linux added a mechanism to disable TSX globally through the kernel command line, and many Linux distributions now default to tsx=off. This makes existing CPU models that have HLE and RTM enabled not usable anymore. Add new versions of all CPU models that have the HLE and RTM features enabled, that can be used when TSX is disabled in the host system. References: [1] TAA, TSX asynchronous Abort: https://software.intel.com/security-software-guidance/insights/deep-dive-intel-transactional-synchronization-extensions-intel-tsx-asynchronous-abort https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2019-11-21 16:35:05 +01:00
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alpha	target/alpha: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
arm	target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY	2019-11-19 13:20:28 +00:00
cris	cputlb: ensure _cmmu helper functions follow the naming standard	2019-10-28 15:12:38 +00:00
hppa	target/hppa: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
i386	i386: Add new versions of Skylake/Cascadelake/Icelake without TSX	2019-11-21 16:35:05 +01:00
lm32	Monitor patches for 2019-08-21	2019-08-22 10:31:21 +01:00
m68k	target/m68k: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
microblaze	target/microblaze: Plug temp leak around eval_cond_jmp()	2019-11-12 16:35:26 +01:00
mips	target/mips: Refactor handling of vector compare 'less than' (signed) instructions	2019-10-25 18:37:01 +02:00
moxie	hw/core: Move cpu.c, cpu.h from qom/ to hw/core/	2019-08-21 13:24:01 +02:00
nios2	Monitor patches for 2019-08-21	2019-08-22 10:31:21 +01:00
openrisc	target/openrisc: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
ppc	spapr/kvm: Set default cpu model for all machine classes	2019-11-18 11:50:39 +01:00
riscv	target/riscv: Remove atomic accesses to MIP CSR	2019-11-14 09:53:28 -08:00
s390x	s390x/kvm: Set default cpu model for all machine classes	2019-10-21 18:03:08 +02:00
sh4	target/sh4: fetch code with translator_ld	2019-10-28 15:12:38 +00:00
sparc	target/sparc: Define an enumeration for accessing env->regwptr	2019-11-06 13:35:25 +01:00
tilegx	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
tricore	tcg: TCGMemOp is now accelerator independent MemOp	2019-09-03 08:30:38 -07:00
unicore32	Monitor patches for 2019-08-21	2019-08-22 10:31:21 +01:00
xtensa	target/xtensa: fetch code with translator_ld	2019-10-28 15:12:38 +00:00