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Peter Maydell 5c6295a45b target-arm queue: 
* Add new mps3-an547 board
  * target/arm: Restrict v7A TCG cpus to TCG accel
  * Implement a Xilinx CSU DMA model
  * hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210310' into staging

target-arm queue:
 * Add new mps3-an547 board
 * target/arm: Restrict v7A TCG cpus to TCG accel
 * Implement a Xilinx CSU DMA model
 * hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()

# gpg: Signature made Wed 10 Mar 2021 13:56:20 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210310: (54 commits)
  hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
  hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
  hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
  hw/ssi: xilinx_spips: Clean up coding convention issues
  hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
  hw/arm: xlnx-zynqmp: Clean up coding convention issues
  hw/dma: Implement a Xilinx CSU DMA model
  target/arm: Restrict v7A TCG cpus to TCG accel
  tests/qtest/sse-timer-test: Test counter scaling changes
  tests/qtest/sse-timer-test: Test the system timer
  tests/qtest/sse-timer-test: Add simple test of the SSE counter
  docs/system/arm/mps2.rst: Document the new mps3-an547 board
  hw/arm/mps2-tz: Add new mps3-an547 board
  hw/arm/mps2-tz: Make initsvtor0 setting board-specific
  hw/arm/mps2-tz: Support running APB peripherals on different clock
  hw/misc/mps2-scc: Implement changes for AN547
  hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
  hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
  hw/arm/mps2-tz: Make UART overflow IRQ board-specific
  hw/arm/armsse: Add SSE-300 support
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 		2021-03-10 13:57:31 +00:00
..
Kconfig hw/mips: Add Loongson-3 machine support 2021-01-04 23:36:03 +01:00
bootloader.c hw/mips: Add a bootloader helper 2021-02-21 18:41:04 +01:00
boston.c hw/mips/boston: Use bootloader helper to set GCRs 2021-02-21 18:41:46 +01:00
cps.c clock: Add ClockEvent parameter to callbacks 2021-03-08 17:20:01 +00:00
fuloong2e.c vt82c686: Move creation of ISA devices to the ISA bridge 2021-02-21 19:42:34 +01:00
fw_cfg.c hw/mips: Implement fw_cfg_arch_key_name() 2021-01-04 23:32:27 +01:00
fw_cfg.h hw/mips: Implement fw_cfg_arch_key_name() 2021-01-04 23:32:27 +01:00
gt64xxx_pci.c hw: Use the PCI_SLOT() macro from 'hw/pci/pci.h' 2021-01-04 23:24:44 +01:00
jazz.c esp: rename existing ESP QOM type to SYSBUS_ESP 2021-03-07 10:39:05 +00:00
loongson3_bootp.c hw/mips: Add Loongson-3 boot parameter helpers 2021-01-04 23:33:38 +01:00
loongson3_bootp.h hw/mips: loongson3: Drop 'struct MemmapEntry' 2021-02-21 14:22:09 +01:00
loongson3_virt.c hw/mips: loongson3: Drop 'struct MemmapEntry' 2021-02-21 14:22:09 +01:00
malta.c hw/mips: Use address translation helper to handle ENVP_ADDR 2021-01-04 23:36:03 +01:00
meson.build hw/mips: Add a bootloader helper 2021-02-21 18:41:04 +01:00
mips_int.c hw/mips: Add CPU IRQ3 delivery for KVM 2020-06-01 13:28:21 +02:00
mipssim.c hw/mips: Make bootloader addresses unsigned 2021-01-04 23:36:03 +01:00
trace-events trace-events: Fix attribution of trace points to source 2020-09-09 17:17:58 +01:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00