c412a48d4d
Add -numa hmat-cache option to provide Memory Side Cache Information. These memory attributes help to build Memory Side Cache Information Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT). Before using hmat-cache option, enable HMAT with -machine hmat=on. Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Liu Jingqi <jingqi.liu@intel.com> Signed-off-by: Tao Xu <tao3.xu@intel.com> Message-Id: <20191213011929.2520-4-tao3.xu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
117 lines
3.3 KiB
C
117 lines
3.3 KiB
C
#ifndef SYSEMU_NUMA_H
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#define SYSEMU_NUMA_H
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#include "qemu/bitmap.h"
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#include "qapi/qapi-types-machine.h"
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#include "exec/cpu-common.h"
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struct CPUArchId;
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#define MAX_NODES 128
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#define NUMA_NODE_UNASSIGNED MAX_NODES
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#define NUMA_DISTANCE_MIN 10
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#define NUMA_DISTANCE_DEFAULT 20
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#define NUMA_DISTANCE_MAX 254
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#define NUMA_DISTANCE_UNREACHABLE 255
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/* the value of AcpiHmatLBInfo flags */
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enum {
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HMAT_LB_MEM_MEMORY = 0,
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HMAT_LB_MEM_CACHE_1ST_LEVEL = 1,
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HMAT_LB_MEM_CACHE_2ND_LEVEL = 2,
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HMAT_LB_MEM_CACHE_3RD_LEVEL = 3,
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HMAT_LB_LEVELS /* must be the last entry */
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};
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/* the value of AcpiHmatLBInfo data type */
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enum {
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HMAT_LB_DATA_ACCESS_LATENCY = 0,
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HMAT_LB_DATA_READ_LATENCY = 1,
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HMAT_LB_DATA_WRITE_LATENCY = 2,
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HMAT_LB_DATA_ACCESS_BANDWIDTH = 3,
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HMAT_LB_DATA_READ_BANDWIDTH = 4,
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HMAT_LB_DATA_WRITE_BANDWIDTH = 5,
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HMAT_LB_TYPES /* must be the last entry */
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};
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#define UINT16_BITS 16
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struct NodeInfo {
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uint64_t node_mem;
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struct HostMemoryBackend *node_memdev;
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bool present;
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bool has_cpu;
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uint8_t lb_info_provided;
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uint16_t initiator;
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uint8_t distance[MAX_NODES];
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};
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struct NumaNodeMem {
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uint64_t node_mem;
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uint64_t node_plugged_mem;
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};
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struct HMAT_LB_Data {
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uint8_t initiator;
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uint8_t target;
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uint64_t data;
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};
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typedef struct HMAT_LB_Data HMAT_LB_Data;
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struct HMAT_LB_Info {
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/* Indicates it's memory or the specified level memory side cache. */
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uint8_t hierarchy;
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/* Present the type of data, access/read/write latency or bandwidth. */
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uint8_t data_type;
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/* The range bitmap of bandwidth for calculating common base */
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uint64_t range_bitmap;
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/* The common base unit for latencies or bandwidths */
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uint64_t base;
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/* Array to store the latencies or bandwidths */
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GArray *list;
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};
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typedef struct HMAT_LB_Info HMAT_LB_Info;
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struct NumaState {
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/* Number of NUMA nodes */
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int num_nodes;
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/* Allow setting NUMA distance for different NUMA nodes */
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bool have_numa_distance;
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/* Detect if HMAT support is enabled. */
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bool hmat_enabled;
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/* NUMA nodes information */
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NodeInfo nodes[MAX_NODES];
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/* NUMA nodes HMAT Locality Latency and Bandwidth Information */
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HMAT_LB_Info *hmat_lb[HMAT_LB_LEVELS][HMAT_LB_TYPES];
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/* Memory Side Cache Information Structure */
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NumaHmatCacheOptions *hmat_cache[MAX_NODES][HMAT_LB_LEVELS];
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};
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typedef struct NumaState NumaState;
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void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp);
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void parse_numa_opts(MachineState *ms);
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void parse_numa_hmat_lb(NumaState *numa_state, NumaHmatLBOptions *node,
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Error **errp);
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void parse_numa_hmat_cache(MachineState *ms, NumaHmatCacheOptions *node,
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Error **errp);
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void numa_complete_configuration(MachineState *ms);
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void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms);
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extern QemuOptsList qemu_numa_opts;
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void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
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int nb_nodes, ram_addr_t size);
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void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
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int nb_nodes, ram_addr_t size);
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void numa_cpu_pre_plug(const struct CPUArchId *slot, DeviceState *dev,
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Error **errp);
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#endif
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