00f05c02f9
An option on real hardware when embedding a DMA engine into a peripheral is to make the peripheral control the engine through a custom DMA control (hardware) interface between the two. Software drivers in this scenario configure and trigger DMA operations through the controlling peripheral's register API (for example, writing a specific bit in a register could propagate down to a transfer start signal on the DMA control interface). At the same time the status, results and interrupts for the transfer might still be intended to be read and caught through the DMA engine's register API (and signals). This patch adds a class 'read' method for allowing to start read transfers from peripherals embedding and controlling the Xilinx CSU DMA engine as in above scenario. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-6-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
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* Xilinx Platform CSU Stream DMA emulation
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*
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* This implementation is based on
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* https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef XLNX_CSU_DMA_H
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#define XLNX_CSU_DMA_H
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "hw/ptimer.h"
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#include "hw/stream.h"
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#define TYPE_XLNX_CSU_DMA "xlnx.csu_dma"
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#define XLNX_CSU_DMA_R_MAX (0x2c / 4)
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typedef struct XlnxCSUDMA {
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SysBusDevice busdev;
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MemoryRegion iomem;
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MemTxAttrs attr;
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MemoryRegion *dma_mr;
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AddressSpace dma_as;
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qemu_irq irq;
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StreamSink *tx_dev; /* Used as generic StreamSink */
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ptimer_state *src_timer;
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uint16_t width;
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bool is_dst;
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bool r_size_last_word;
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StreamCanPushNotifyFn notify;
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void *notify_opaque;
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uint32_t regs[XLNX_CSU_DMA_R_MAX];
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RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX];
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} XlnxCSUDMA;
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OBJECT_DECLARE_TYPE(XlnxCSUDMA, XlnxCSUDMAClass, XLNX_CSU_DMA)
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struct XlnxCSUDMAClass {
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SysBusDeviceClass parent_class;
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/*
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* read: Start a read transfer on a Xilinx CSU DMA engine
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*
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* @s: the Xilinx CSU DMA engine to start the transfer on
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* @addr: the address to read
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* @len: the number of bytes to read at 'addr'
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*
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* @return a MemTxResult indicating whether the operation succeeded ('len'
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* bytes were read) or failed.
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*/
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MemTxResult (*read)(XlnxCSUDMA *s, hwaddr addr, uint32_t len);
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};
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#endif
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