qemu-e2k/target
David Hildenbrand 9be6fa99d6 s390x/tcg: Introduce tcg_s390_vector_exception()
Handling is similar to data exceptions, however we can always store the
VXC into the lowore and the FPC:

z14 PoP, 6-20, "Vector-Exception Code"
    When a vector-processing exception causes a pro-
    gram interruption, a vector-exception code (VXC) is
    stored at location 147, and zeros are stored at loca-
    tions 144-146. The VXC is also placed in the DXC
    field of the floating-point-control (FPC) register if bit
    45 of control register 0 is one. When bit 45 of control
    register 0 is zero and bit 46 of control register 0 is
    one, the DXC field of the FPC register and the con-
    tents of storage at location 147 are unpredictable.

Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07 14:53:25 +02:00
..
alpha target/alpha: Fix user-only floating-point exceptions 2019-05-19 07:30:03 -07:00
arm target/arm: correct return values for WRITE/READ in arm-semi 2019-05-28 10:28:51 +01:00
cris Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
hppa tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
i386 i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor 2019-06-03 14:03:01 +02:00
lm32 semihosting: move semihosting configuration into its own directory 2019-05-28 10:28:50 +01:00
m68k semihosting: move semihosting configuration into its own directory 2019-05-28 10:28:50 +01:00
microblaze tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
mips target/mips: Unroll loops in helpers for MSA logic instructions 2019-06-07 11:53:07 +02:00
moxie tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
nios2 semihosting: move semihosting configuration into its own directory 2019-05-28 10:28:50 +01:00
openrisc tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
ppc spapr/xive: add KVM support 2019-05-29 11:39:45 +10:00
riscv target/riscv: Only flush TLB if SATP.ASID changes 2019-05-24 12:09:25 -07:00
s390x s390x/tcg: Introduce tcg_s390_vector_exception() 2019-06-07 14:53:25 +02:00
sh4 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
sparc Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
tilegx target/tilegx: Convert to CPUClass::tlb_fill 2019-05-10 11:12:50 -07:00
tricore Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
unicore32 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
xtensa semihosting: move semihosting configuration into its own directory 2019-05-28 10:28:50 +01:00