65 lines
2.2 KiB
C
65 lines
2.2 KiB
C
/*
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* Vectored Interrupt Controller for nios2 processor
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*
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* Copyright (c) 2022 Neuroblade
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*
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* Interface:
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* QOM property "cpu": link to the Nios2 CPU (must be set)
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* Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines
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* IRQ should be connected to nios2 IRQ0.
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*
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* Reference: "Embedded Peripherals IP User Guide
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* for Intel® Quartus® Prime Design Suite: 21.4"
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* Chapter 38 "Vectored Interrupt Controller Core"
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* See: https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/vectored-interrupt-controller-core.html
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_INTC_NIOS2_VIC_H
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#define HW_INTC_NIOS2_VIC_H
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#define TYPE_NIOS2_VIC "nios2-vic"
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OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC)
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#define NIOS2_VIC_MAX_IRQ 32
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struct Nios2VIC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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qemu_irq output_int;
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/* properties */
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CPUState *cpu;
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MemoryRegion csr;
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uint32_t int_config[NIOS2_VIC_MAX_IRQ];
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uint32_t vic_config;
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uint32_t int_raw_status;
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uint32_t int_enable;
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uint32_t sw_int;
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uint32_t vic_status;
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uint32_t vec_tbl_base;
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uint32_t vec_tbl_addr;
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};
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#endif /* HW_INTC_NIOS2_VIC_H */
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