02a5a4a877
Make timer/CCOUNT tests conditional on the presence of timer option and number of configured timers. Don't use hard coded interrupt levels for timers, use configured values. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
258 lines
5.0 KiB
ArmAsm
258 lines
5.0 KiB
ArmAsm
#include "macros.inc"
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#define CCOUNT_SHIFT 4
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#define WAIT_LOOPS 20
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#define level1 kernel
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#define INTERRUPT_LEVEL(n) glue3(XCHAL_INT, n, _LEVEL)
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.macro make_ccount_delta target, delta
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rsr \delta, ccount
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rsr \target, ccount
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sub \delta, \target, \delta
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slli \delta, \delta, CCOUNT_SHIFT
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add \target, \target, \delta
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.endm
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test_suite timer
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#if XCHAL_HAVE_CCOUNT
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test ccount
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rsr a3, ccount
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rsr a4, ccount
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assert ne, a3, a4
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test_end
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test ccount_write
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rsr a3, ccount
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rsr a4, ccount
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sub a4, a4, a3
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movi a2, 0x12345678
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wsr a2, ccount
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esync
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rsr a3, ccount
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sub a3, a3, a2
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slli a4, a4, 2
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assert ltu, a3, a4
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test_end
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#if XCHAL_NUM_TIMERS
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test ccount_update_deadline
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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#if XCHAL_NUM_TIMERS > 1
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wsr a2, ccompare1
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#endif
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#if XCHAL_NUM_TIMERS > 2
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wsr a2, ccompare2
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#endif
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movi a2, 0x12345678
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wsr a2, ccompare0
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rsr a3, interrupt
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assert eqi, a3, 0
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movi a2, 0x12345677
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wsr a2, ccount
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esync
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nop
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rsr a2, interrupt
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movi a3, 1 << XCHAL_TIMER0_INTERRUPT
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assert eq, a2, a3
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test_end
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test ccompare
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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#if XCHAL_NUM_TIMERS > 1
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wsr a2, ccompare1
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#endif
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#if XCHAL_NUM_TIMERS > 2
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wsr a2, ccompare2
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#endif
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make_ccount_delta a2, a15
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wsr a2, ccompare0
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1:
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rsr a3, interrupt
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rsr a4, ccount
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rsr a5, interrupt
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sub a4, a4, a2
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bgez a4, 2f
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assert eqi, a3, 0
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j 1b
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2:
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assert nei, a5, 0
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test_end
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#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
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test ccompare0_interrupt
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set_vector kernel, 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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#if XCHAL_NUM_TIMERS > 1
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wsr a2, ccompare1
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#endif
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#if XCHAL_NUM_TIMERS > 2
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wsr a2, ccompare2
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#endif
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movi a3, WAIT_LOOPS
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make_ccount_delta a2, a15
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wsr a2, ccompare0
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 1 << XCHAL_TIMER0_INTERRUPT
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wsr a2, intenable
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rsil a2, 0
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loop a3, 1f
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nop
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1:
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test_fail
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2:
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rsr a2, exccause
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assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
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test_end
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#endif
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#if XCHAL_NUM_TIMERS > 1
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test ccompare1_interrupt
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set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)), 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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wsr a2, ccompare0
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#if XCHAL_NUM_TIMERS > 2
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wsr a2, ccompare2
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#endif
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movi a3, WAIT_LOOPS
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make_ccount_delta a2, a15
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wsr a2, ccompare1
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 1 << XCHAL_TIMER1_INTERRUPT
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wsr a2, intenable
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rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1
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loop a3, 1f
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nop
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1:
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test_fail
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2:
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test_end
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#endif
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#if XCHAL_NUM_TIMERS > 2
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test ccompare2_interrupt
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set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)), 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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wsr a2, ccompare0
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wsr a2, ccompare1
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movi a3, WAIT_LOOPS
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make_ccount_delta a2, a15
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wsr a2, ccompare2
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 1 << XCHAL_TIMER2_INTERRUPT
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wsr a2, intenable
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rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1
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loop a3, 1f
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nop
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1:
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test_fail
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2:
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test_end
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#endif
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test ccompare_interrupt_masked
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set_vector kernel, 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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#if XCHAL_NUM_TIMERS > 2
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wsr a2, ccompare2
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#endif
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movi a3, 2 * WAIT_LOOPS
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make_ccount_delta a2, a15
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#if XCHAL_NUM_TIMERS > 1
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wsr a2, ccompare1
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#endif
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add a2, a2, a15
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wsr a2, ccompare0
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 1 << XCHAL_TIMER0_INTERRUPT
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wsr a2, intenable
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rsil a2, 0
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loop a3, 1f
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nop
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1:
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test_fail
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2:
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rsr a2, exccause
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assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
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test_end
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test ccompare_interrupt_masked_waiti
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set_vector kernel, 2f
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movi a2, 0
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wsr a2, intenable
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rsr a2, interrupt
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wsr a2, intclear
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movi a2, 0
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#if XCHAL_NUM_TIMERS > 2
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wsr a2, ccompare2
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#endif
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movi a3, 2 * WAIT_LOOPS
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make_ccount_delta a2, a15
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#if XCHAL_NUM_TIMERS > 1
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wsr a2, ccompare1
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#endif
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add a2, a2, a15
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wsr a2, ccompare0
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rsync
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rsr a2, interrupt
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assert eqi, a2, 0
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movi a2, 1 << XCHAL_TIMER0_INTERRUPT
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wsr a2, intenable
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waiti 0
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test_fail
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2:
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rsr a2, exccause
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assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
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test_end
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#endif
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#endif
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test_suite_end
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