527 lines
15 KiB
C
527 lines
15 KiB
C
/*
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* Luminary Micro Stellaris Ethernet Controller
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*
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* Copyright (c) 2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "net/net.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include <zlib.h>
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#include "qom/object.h"
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//#define DEBUG_STELLARIS_ENET 1
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#ifdef DEBUG_STELLARIS_ENET
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#define DPRINTF(fmt, ...) \
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do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
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#endif
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#define SE_INT_RX 0x01
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#define SE_INT_TXER 0x02
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#define SE_INT_TXEMP 0x04
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#define SE_INT_FOV 0x08
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#define SE_INT_RXER 0x10
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#define SE_INT_MD 0x20
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#define SE_INT_PHY 0x40
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#define SE_RCTL_RXEN 0x01
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#define SE_RCTL_AMUL 0x02
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#define SE_RCTL_PRMS 0x04
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#define SE_RCTL_BADCRC 0x08
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#define SE_RCTL_RSTFIFO 0x10
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#define SE_TCTL_TXEN 0x01
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#define SE_TCTL_PADEN 0x02
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#define SE_TCTL_CRC 0x04
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#define SE_TCTL_DUPLEX 0x08
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#define TYPE_STELLARIS_ENET "stellaris_enet"
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OBJECT_DECLARE_SIMPLE_TYPE(stellaris_enet_state, STELLARIS_ENET)
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typedef struct {
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uint8_t data[2048];
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uint32_t len;
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} StellarisEnetRxFrame;
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struct stellaris_enet_state {
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SysBusDevice parent_obj;
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uint32_t ris;
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uint32_t im;
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uint32_t rctl;
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uint32_t tctl;
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uint32_t thr;
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uint32_t mctl;
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uint32_t mdv;
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uint32_t mtxd;
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uint32_t mrxd;
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uint32_t np;
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uint32_t tx_fifo_len;
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uint8_t tx_fifo[2048];
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/* Real hardware has a 2k fifo, which works out to be at most 31 packets.
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We implement a full 31 packet fifo. */
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StellarisEnetRxFrame rx[31];
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uint32_t rx_fifo_offset;
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uint32_t next_packet;
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NICState *nic;
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NICConf conf;
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qemu_irq irq;
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MemoryRegion mmio;
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};
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static const VMStateDescription vmstate_rx_frame = {
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.name = "stellaris_enet/rx_frame",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8_ARRAY(data, StellarisEnetRxFrame, 2048),
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VMSTATE_UINT32(len, StellarisEnetRxFrame),
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VMSTATE_END_OF_LIST()
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}
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};
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static int stellaris_enet_post_load(void *opaque, int version_id)
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{
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stellaris_enet_state *s = opaque;
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int i;
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/* Sanitize inbound state. Note that next_packet is an index but
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* np is a size; hence their valid upper bounds differ.
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*/
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if (s->next_packet >= ARRAY_SIZE(s->rx)) {
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return -1;
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}
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if (s->np > ARRAY_SIZE(s->rx)) {
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return -1;
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}
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for (i = 0; i < ARRAY_SIZE(s->rx); i++) {
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if (s->rx[i].len > ARRAY_SIZE(s->rx[i].data)) {
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return -1;
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}
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}
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if (s->rx_fifo_offset > ARRAY_SIZE(s->rx[0].data) - 4) {
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return -1;
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}
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if (s->tx_fifo_len > ARRAY_SIZE(s->tx_fifo)) {
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return -1;
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}
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return 0;
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}
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static const VMStateDescription vmstate_stellaris_enet = {
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.name = "stellaris_enet",
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.version_id = 2,
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.minimum_version_id = 2,
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.post_load = stellaris_enet_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ris, stellaris_enet_state),
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VMSTATE_UINT32(im, stellaris_enet_state),
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VMSTATE_UINT32(rctl, stellaris_enet_state),
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VMSTATE_UINT32(tctl, stellaris_enet_state),
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VMSTATE_UINT32(thr, stellaris_enet_state),
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VMSTATE_UINT32(mctl, stellaris_enet_state),
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VMSTATE_UINT32(mdv, stellaris_enet_state),
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VMSTATE_UINT32(mtxd, stellaris_enet_state),
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VMSTATE_UINT32(mrxd, stellaris_enet_state),
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VMSTATE_UINT32(np, stellaris_enet_state),
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VMSTATE_UINT32(tx_fifo_len, stellaris_enet_state),
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VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048),
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VMSTATE_STRUCT_ARRAY(rx, stellaris_enet_state, 31, 1,
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vmstate_rx_frame, StellarisEnetRxFrame),
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VMSTATE_UINT32(rx_fifo_offset, stellaris_enet_state),
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VMSTATE_UINT32(next_packet, stellaris_enet_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static void stellaris_enet_update(stellaris_enet_state *s)
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{
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qemu_set_irq(s->irq, (s->ris & s->im) != 0);
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}
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/* Return the data length of the packet currently being assembled
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* in the TX fifo.
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*/
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static inline int stellaris_txpacket_datalen(stellaris_enet_state *s)
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{
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return s->tx_fifo[0] | (s->tx_fifo[1] << 8);
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}
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/* Return true if the packet currently in the TX FIFO is complete,
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* ie the FIFO holds enough bytes for the data length, ethernet header,
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* payload and optionally CRC.
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*/
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static inline bool stellaris_txpacket_complete(stellaris_enet_state *s)
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{
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int framelen = stellaris_txpacket_datalen(s);
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framelen += 16;
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if (!(s->tctl & SE_TCTL_CRC)) {
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framelen += 4;
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}
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/* Cover the corner case of a 2032 byte payload with auto-CRC disabled:
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* this requires more bytes than will fit in the FIFO. It's not totally
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* clear how the h/w handles this, but if using threshold-based TX
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* it will definitely try to transmit something.
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*/
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framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo));
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return s->tx_fifo_len >= framelen;
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}
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/* Return true if the TX FIFO threshold is enabled and the FIFO
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* has filled enough to reach it.
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*/
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static inline bool stellaris_tx_thr_reached(stellaris_enet_state *s)
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{
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return (s->thr < 0x3f &&
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(s->tx_fifo_len >= 4 * (s->thr * 8 + 1)));
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}
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/* Send the packet currently in the TX FIFO */
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static void stellaris_enet_send(stellaris_enet_state *s)
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{
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int framelen = stellaris_txpacket_datalen(s);
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/* Ethernet header is in the FIFO but not in the datacount.
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* We don't implement explicit CRC, so just ignore any
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* CRC value in the FIFO.
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*/
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framelen += 14;
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if ((s->tctl & SE_TCTL_PADEN) && framelen < 60) {
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memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen);
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framelen = 60;
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}
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/* This MIN will have no effect unless the FIFO data is corrupt
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* (eg bad data from an incoming migration); otherwise the check
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* on the datalen at the start of writing the data into the FIFO
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* will have caught this. Silently write a corrupt half-packet,
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* which is what the hardware does in FIFO underrun situations.
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*/
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framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2);
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qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen);
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s->tx_fifo_len = 0;
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s->ris |= SE_INT_TXEMP;
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stellaris_enet_update(s);
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DPRINTF("Done TX\n");
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}
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/* TODO: Implement MAC address filtering. */
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static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
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{
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stellaris_enet_state *s = qemu_get_nic_opaque(nc);
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int n;
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uint8_t *p;
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uint32_t crc;
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if ((s->rctl & SE_RCTL_RXEN) == 0)
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return -1;
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if (s->np >= 31) {
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return 0;
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}
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DPRINTF("Received packet len=%zu\n", size);
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n = s->next_packet + s->np;
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if (n >= 31)
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n -= 31;
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if (size >= sizeof(s->rx[n].data) - 6) {
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/* If the packet won't fit into the
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* emulated 2K RAM, this is reported
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* as a FIFO overrun error.
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*/
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s->ris |= SE_INT_FOV;
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stellaris_enet_update(s);
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return -1;
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}
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s->np++;
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s->rx[n].len = size + 6;
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p = s->rx[n].data;
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*(p++) = (size + 6);
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*(p++) = (size + 6) >> 8;
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memcpy (p, buf, size);
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p += size;
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crc = crc32(~0, buf, size);
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*(p++) = crc;
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*(p++) = crc >> 8;
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*(p++) = crc >> 16;
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*(p++) = crc >> 24;
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/* Clear the remaining bytes in the last word. */
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if ((size & 3) != 2) {
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memset(p, 0, (6 - size) & 3);
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}
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s->ris |= SE_INT_RX;
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stellaris_enet_update(s);
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return size;
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}
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static int stellaris_enet_can_receive(stellaris_enet_state *s)
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{
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return (s->np < 31);
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}
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static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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stellaris_enet_state *s = (stellaris_enet_state *)opaque;
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uint32_t val;
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switch (offset) {
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case 0x00: /* RIS */
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DPRINTF("IRQ status %02x\n", s->ris);
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return s->ris;
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case 0x04: /* IM */
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return s->im;
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case 0x08: /* RCTL */
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return s->rctl;
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case 0x0c: /* TCTL */
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return s->tctl;
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case 0x10: /* DATA */
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{
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uint8_t *rx_fifo;
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if (s->np == 0) {
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BADF("RX underflow\n");
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return 0;
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}
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rx_fifo = s->rx[s->next_packet].data + s->rx_fifo_offset;
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val = rx_fifo[0] | (rx_fifo[1] << 8) | (rx_fifo[2] << 16)
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| (rx_fifo[3] << 24);
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s->rx_fifo_offset += 4;
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if (s->rx_fifo_offset >= s->rx[s->next_packet].len) {
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s->rx_fifo_offset = 0;
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s->next_packet++;
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if (s->next_packet >= 31)
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s->next_packet = 0;
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s->np--;
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DPRINTF("RX done np=%d\n", s->np);
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if (!s->np && stellaris_enet_can_receive(s)) {
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qemu_flush_queued_packets(qemu_get_queue(s->nic));
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}
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}
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return val;
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}
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case 0x14: /* IA0 */
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return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
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| (s->conf.macaddr.a[2] << 16)
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| ((uint32_t)s->conf.macaddr.a[3] << 24);
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case 0x18: /* IA1 */
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return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
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case 0x1c: /* THR */
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return s->thr;
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case 0x20: /* MCTL */
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return s->mctl;
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case 0x24: /* MDV */
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return s->mdv;
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case 0x28: /* MADD */
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return 0;
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case 0x2c: /* MTXD */
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return s->mtxd;
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case 0x30: /* MRXD */
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return s->mrxd;
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case 0x34: /* NP */
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return s->np;
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case 0x38: /* TR */
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return 0;
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case 0x3c: /* Undocumented: Timestamp? */
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return 0;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_rd%d: Illegal register"
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" 0x02%" HWADDR_PRIx "\n",
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size * 8, offset);
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return 0;
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}
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}
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static void stellaris_enet_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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stellaris_enet_state *s = (stellaris_enet_state *)opaque;
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switch (offset) {
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case 0x00: /* IACK */
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s->ris &= ~value;
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DPRINTF("IRQ ack %02" PRIx64 "/%02x\n", value, s->ris);
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stellaris_enet_update(s);
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/* Clearing TXER also resets the TX fifo. */
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if (value & SE_INT_TXER) {
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s->tx_fifo_len = 0;
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}
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break;
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case 0x04: /* IM */
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DPRINTF("IRQ mask %02" PRIx64 "/%02x\n", value, s->ris);
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s->im = value;
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stellaris_enet_update(s);
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break;
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case 0x08: /* RCTL */
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s->rctl = value;
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if (value & SE_RCTL_RSTFIFO) {
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s->np = 0;
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s->rx_fifo_offset = 0;
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stellaris_enet_update(s);
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}
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break;
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case 0x0c: /* TCTL */
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s->tctl = value;
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break;
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case 0x10: /* DATA */
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if (s->tx_fifo_len == 0) {
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/* The first word is special, it contains the data length */
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int framelen = value & 0xffff;
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if (framelen > 2032) {
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DPRINTF("TX frame too long (%d)\n", framelen);
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s->ris |= SE_INT_TXER;
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stellaris_enet_update(s);
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break;
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}
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}
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if (s->tx_fifo_len + 4 <= ARRAY_SIZE(s->tx_fifo)) {
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s->tx_fifo[s->tx_fifo_len++] = value;
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s->tx_fifo[s->tx_fifo_len++] = value >> 8;
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s->tx_fifo[s->tx_fifo_len++] = value >> 16;
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s->tx_fifo[s->tx_fifo_len++] = value >> 24;
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}
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if (stellaris_tx_thr_reached(s) && stellaris_txpacket_complete(s)) {
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stellaris_enet_send(s);
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}
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break;
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case 0x14: /* IA0 */
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s->conf.macaddr.a[0] = value;
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s->conf.macaddr.a[1] = value >> 8;
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s->conf.macaddr.a[2] = value >> 16;
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s->conf.macaddr.a[3] = value >> 24;
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break;
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case 0x18: /* IA1 */
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s->conf.macaddr.a[4] = value;
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s->conf.macaddr.a[5] = value >> 8;
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break;
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case 0x1c: /* THR */
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s->thr = value;
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break;
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case 0x20: /* MCTL */
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/* TODO: MII registers aren't modelled.
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* Clear START, indicating that the operation completes immediately.
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*/
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s->mctl = value & ~1;
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break;
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case 0x24: /* MDV */
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s->mdv = value;
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break;
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case 0x28: /* MADD */
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/* ignored. */
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break;
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case 0x2c: /* MTXD */
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s->mtxd = value & 0xff;
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break;
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case 0x38: /* TR */
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if (value & 1) {
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stellaris_enet_send(s);
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}
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break;
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case 0x30: /* MRXD */
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case 0x34: /* NP */
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/* Ignored. */
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case 0x3c: /* Undocuented: Timestamp? */
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/* Ignored. */
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "stellaris_enet_wr%d: Illegal register "
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"0x02%" HWADDR_PRIx " = 0x%" PRIx64 "\n",
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size * 8, offset, value);
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}
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}
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static const MemoryRegionOps stellaris_enet_ops = {
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.read = stellaris_enet_read,
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.write = stellaris_enet_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void stellaris_enet_reset(DeviceState *dev)
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{
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stellaris_enet_state *s = STELLARIS_ENET(dev);
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s->mdv = 0x80;
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s->rctl = SE_RCTL_BADCRC;
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s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
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| SE_INT_TXER | SE_INT_RX;
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s->thr = 0x3f;
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s->tx_fifo_len = 0;
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}
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static NetClientInfo net_stellaris_enet_info = {
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.type = NET_CLIENT_DRIVER_NIC,
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.size = sizeof(NICState),
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.receive = stellaris_enet_receive,
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};
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static void stellaris_enet_realize(DeviceState *dev, Error **errp)
|
|
{
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|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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|
stellaris_enet_state *s = STELLARIS_ENET(dev);
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|
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memory_region_init_io(&s->mmio, OBJECT(s), &stellaris_enet_ops, s,
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|
"stellaris_enet", 0x1000);
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|
sysbus_init_mmio(sbd, &s->mmio);
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sysbus_init_irq(sbd, &s->irq);
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|
qemu_macaddr_default_if_unset(&s->conf.macaddr);
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|
|
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s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf,
|
|
object_get_typename(OBJECT(dev)), dev->id, s);
|
|
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
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|
}
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|
|
|
static Property stellaris_enet_properties[] = {
|
|
DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void stellaris_enet_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = stellaris_enet_realize;
|
|
dc->reset = stellaris_enet_reset;
|
|
device_class_set_props(dc, stellaris_enet_properties);
|
|
dc->vmsd = &vmstate_stellaris_enet;
|
|
}
|
|
|
|
static const TypeInfo stellaris_enet_info = {
|
|
.name = TYPE_STELLARIS_ENET,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(stellaris_enet_state),
|
|
.class_init = stellaris_enet_class_init,
|
|
};
|
|
|
|
static void stellaris_enet_register_types(void)
|
|
{
|
|
type_register_static(&stellaris_enet_info);
|
|
}
|
|
|
|
type_init(stellaris_enet_register_types)
|