0b8fa32f55
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-4-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for hw/usb/dev-hub.c hw/misc/exynos4210_rng.c hw/misc/bcm2835_rng.c hw/misc/aspeed_scu.c hw/display/virtio-vga.c hw/arm/stm32f205_soc.c; ui/cocoa.m fixed up]
366 lines
10 KiB
C
366 lines
10 KiB
C
/*
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* Intel XScale PXA255/270 GPIO controller emulation.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPL.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "hw/arm/pxa.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define PXA2XX_GPIO_BANKS 4
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#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
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#define PXA2XX_GPIO(obj) \
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OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
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typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
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struct PXA2xxGPIOInfo {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq irq0, irq1, irqX;
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int lines;
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int ncpu;
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ARMCPU *cpu;
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/* XXX: GNU C vectors are more suitable */
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uint32_t ilevel[PXA2XX_GPIO_BANKS];
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uint32_t olevel[PXA2XX_GPIO_BANKS];
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uint32_t dir[PXA2XX_GPIO_BANKS];
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uint32_t rising[PXA2XX_GPIO_BANKS];
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uint32_t falling[PXA2XX_GPIO_BANKS];
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uint32_t status[PXA2XX_GPIO_BANKS];
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uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
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uint32_t prev_level[PXA2XX_GPIO_BANKS];
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qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
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qemu_irq read_notify;
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};
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static struct {
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enum {
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GPIO_NONE,
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GPLR,
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GPSR,
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GPCR,
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GPDR,
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GRER,
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GFER,
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GEDR,
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GAFR_L,
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GAFR_U,
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} reg;
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int bank;
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} pxa2xx_gpio_regs[0x200] = {
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[0 ... 0x1ff] = { GPIO_NONE, 0 },
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#define PXA2XX_REG(reg, a0, a1, a2, a3) \
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[a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
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PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
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PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
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PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
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PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
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PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
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PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
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PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
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PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
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PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
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};
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static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
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{
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if (s->status[0] & (1 << 0))
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qemu_irq_raise(s->irq0);
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else
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qemu_irq_lower(s->irq0);
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if (s->status[0] & (1 << 1))
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qemu_irq_raise(s->irq1);
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else
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qemu_irq_lower(s->irq1);
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if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
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qemu_irq_raise(s->irqX);
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else
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qemu_irq_lower(s->irqX);
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}
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/* Bitmap of pins used as standby and sleep wake-up sources. */
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static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
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0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
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};
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static void pxa2xx_gpio_set(void *opaque, int line, int level)
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{
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PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
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CPUState *cpu = CPU(s->cpu);
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int bank;
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uint32_t mask;
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if (line >= s->lines) {
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printf("%s: No GPIO pin %i\n", __func__, line);
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return;
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}
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bank = line >> 5;
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mask = 1U << (line & 31);
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if (level) {
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s->status[bank] |= s->rising[bank] & mask &
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~s->ilevel[bank] & ~s->dir[bank];
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s->ilevel[bank] |= mask;
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} else {
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s->status[bank] |= s->falling[bank] & mask &
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s->ilevel[bank] & ~s->dir[bank];
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s->ilevel[bank] &= ~mask;
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}
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if (s->status[bank] & mask)
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pxa2xx_gpio_irq_update(s);
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/* Wake-up GPIOs */
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if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
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cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
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}
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}
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static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
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uint32_t level, diff;
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int i, bit, line;
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for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
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level = s->olevel[i] & s->dir[i];
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for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
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bit = ctz32(diff);
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line = bit + 32 * i;
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qemu_set_irq(s->handler[line], (level >> bit) & 1);
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}
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s->prev_level[i] = level;
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}
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}
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static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
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uint32_t ret;
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int bank;
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if (offset >= 0x200)
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return 0;
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bank = pxa2xx_gpio_regs[offset].bank;
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switch (pxa2xx_gpio_regs[offset].reg) {
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case GPDR: /* GPIO Pin-Direction registers */
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return s->dir[bank];
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case GPSR: /* GPIO Pin-Output Set registers */
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qemu_log_mask(LOG_GUEST_ERROR,
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"pxa2xx GPIO: read from write only register GPSR\n");
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return 0;
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case GPCR: /* GPIO Pin-Output Clear registers */
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qemu_log_mask(LOG_GUEST_ERROR,
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"pxa2xx GPIO: read from write only register GPCR\n");
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return 0;
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case GRER: /* GPIO Rising-Edge Detect Enable registers */
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return s->rising[bank];
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case GFER: /* GPIO Falling-Edge Detect Enable registers */
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return s->falling[bank];
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case GAFR_L: /* GPIO Alternate Function registers */
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return s->gafr[bank * 2];
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case GAFR_U: /* GPIO Alternate Function registers */
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return s->gafr[bank * 2 + 1];
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case GPLR: /* GPIO Pin-Level registers */
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ret = (s->olevel[bank] & s->dir[bank]) |
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(s->ilevel[bank] & ~s->dir[bank]);
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qemu_irq_raise(s->read_notify);
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return ret;
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case GEDR: /* GPIO Edge Detect Status registers */
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return s->status[bank];
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default:
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hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
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}
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return 0;
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}
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static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
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int bank;
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if (offset >= 0x200)
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return;
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bank = pxa2xx_gpio_regs[offset].bank;
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switch (pxa2xx_gpio_regs[offset].reg) {
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case GPDR: /* GPIO Pin-Direction registers */
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s->dir[bank] = value;
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pxa2xx_gpio_handler_update(s);
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break;
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case GPSR: /* GPIO Pin-Output Set registers */
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s->olevel[bank] |= value;
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pxa2xx_gpio_handler_update(s);
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break;
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case GPCR: /* GPIO Pin-Output Clear registers */
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s->olevel[bank] &= ~value;
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pxa2xx_gpio_handler_update(s);
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break;
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case GRER: /* GPIO Rising-Edge Detect Enable registers */
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s->rising[bank] = value;
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break;
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case GFER: /* GPIO Falling-Edge Detect Enable registers */
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s->falling[bank] = value;
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break;
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case GAFR_L: /* GPIO Alternate Function registers */
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s->gafr[bank * 2] = value;
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break;
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case GAFR_U: /* GPIO Alternate Function registers */
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s->gafr[bank * 2 + 1] = value;
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break;
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case GEDR: /* GPIO Edge Detect Status registers */
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s->status[bank] &= ~value;
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pxa2xx_gpio_irq_update(s);
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break;
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default:
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hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset);
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}
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}
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static const MemoryRegionOps pxa_gpio_ops = {
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.read = pxa2xx_gpio_read,
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.write = pxa2xx_gpio_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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DeviceState *pxa2xx_gpio_init(hwaddr base,
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ARMCPU *cpu, DeviceState *pic, int lines)
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{
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CPUState *cs = CPU(cpu);
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DeviceState *dev;
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dev = qdev_create(NULL, TYPE_PXA2XX_GPIO);
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qdev_prop_set_int32(dev, "lines", lines);
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qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
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qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
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qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
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qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
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return dev;
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}
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static void pxa2xx_gpio_initfn(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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DeviceState *dev = DEVICE(sbd);
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PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
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memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
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s, "pxa2xx-gpio", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq0);
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sysbus_init_irq(sbd, &s->irq1);
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sysbus_init_irq(sbd, &s->irqX);
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}
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static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
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{
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PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
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s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
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qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
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qdev_init_gpio_out(dev, s->handler, s->lines);
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}
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/*
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* Registers a callback to notify on GPLR reads. This normally
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* shouldn't be needed but it is used for the hack on Spitz machines.
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*/
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void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
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{
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PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
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s->read_notify = handler;
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}
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static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
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.name = "pxa2xx-gpio",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
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VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
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VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
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VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
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VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
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VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
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VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
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VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
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VMSTATE_END_OF_LIST(),
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},
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};
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static Property pxa2xx_gpio_properties[] = {
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DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
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DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "PXA2xx GPIO controller";
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dc->props = pxa2xx_gpio_properties;
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dc->vmsd = &vmstate_pxa2xx_gpio_regs;
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dc->realize = pxa2xx_gpio_realize;
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}
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static const TypeInfo pxa2xx_gpio_info = {
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.name = TYPE_PXA2XX_GPIO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PXA2xxGPIOInfo),
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.instance_init = pxa2xx_gpio_initfn,
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.class_init = pxa2xx_gpio_class_init,
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};
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static void pxa2xx_gpio_register_types(void)
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{
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type_register_static(&pxa2xx_gpio_info);
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}
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type_init(pxa2xx_gpio_register_types)
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