edf5ca5dbe
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
#include "qemu/osdep.h"
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#include "hw/pci/slotid_cap.h"
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#include "hw/pci/pci_device.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#define SLOTID_CAP_LENGTH 4
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#define SLOTID_NSLOTS_SHIFT ctz32(PCI_SID_ESR_NSLOTS)
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int slotid_cap_init(PCIDevice *d, int nslots,
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uint8_t chassis,
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unsigned offset,
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Error **errp)
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{
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int cap;
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if (!chassis) {
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error_setg(errp, "Bridge chassis not specified. Each bridge is required"
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" to be assigned a unique chassis id > 0.");
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return -EINVAL;
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}
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if (nslots < 0 || nslots > (PCI_SID_ESR_NSLOTS >> SLOTID_NSLOTS_SHIFT)) {
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/* TODO: error report? */
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return -EINVAL;
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}
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cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset,
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SLOTID_CAP_LENGTH, errp);
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if (cap < 0) {
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return cap;
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}
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/* We make each chassis unique, this way each bridge is First in Chassis */
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d->config[cap + PCI_SID_ESR] = PCI_SID_ESR_FIC |
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(nslots << SLOTID_NSLOTS_SHIFT);
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d->cmask[cap + PCI_SID_ESR] = 0xff;
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d->config[cap + PCI_SID_CHASSIS_NR] = chassis;
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/* Note: Chassis number register is non-volatile,
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so we don't reset it. */
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/* TODO: store in eeprom? */
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d->wmask[cap + PCI_SID_CHASSIS_NR] = 0xff;
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d->cap_present |= QEMU_PCI_CAP_SLOTID;
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return 0;
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}
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void slotid_cap_cleanup(PCIDevice *d)
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{
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/* TODO: cleanup config space? */
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d->cap_present &= ~QEMU_PCI_CAP_SLOTID;
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}
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