363 lines
9.5 KiB
C
363 lines
9.5 KiB
C
/*
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* Info about, and flushing the host cpu caches.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/cacheflush.h"
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#include "qemu/cacheinfo.h"
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#include "qemu/bitops.h"
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#include "qemu/host-utils.h"
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#include "qemu/atomic.h"
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int qemu_icache_linesize = 0;
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int qemu_icache_linesize_log;
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int qemu_dcache_linesize = 0;
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int qemu_dcache_linesize_log;
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/*
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* Operating system specific cache detection mechanisms.
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*/
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#if defined(_WIN32)
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static void sys_cache_info(int *isize, int *dsize)
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{
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SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf;
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DWORD size = 0;
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BOOL success;
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size_t i, n;
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/*
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* Check for the required buffer size first. Note that if the zero
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* size we use for the probe results in success, then there is no
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* data available; fail in that case.
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*/
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success = GetLogicalProcessorInformation(0, &size);
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if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
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return;
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}
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n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
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size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
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buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n);
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if (!GetLogicalProcessorInformation(buf, &size)) {
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goto fail;
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}
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for (i = 0; i < n; i++) {
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if (buf[i].Relationship == RelationCache
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&& buf[i].Cache.Level == 1) {
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switch (buf[i].Cache.Type) {
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case CacheUnified:
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*isize = *dsize = buf[i].Cache.LineSize;
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break;
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case CacheInstruction:
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*isize = buf[i].Cache.LineSize;
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break;
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case CacheData:
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*dsize = buf[i].Cache.LineSize;
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break;
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default:
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break;
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}
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}
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}
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fail:
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g_free(buf);
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}
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#elif defined(CONFIG_DARWIN)
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# include <sys/sysctl.h>
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static void sys_cache_info(int *isize, int *dsize)
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{
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/* There's only a single sysctl for both I/D cache line sizes. */
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long size;
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size_t len = sizeof(size);
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if (!sysctlbyname("hw.cachelinesize", &size, &len, NULL, 0)) {
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*isize = *dsize = size;
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}
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}
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#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
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# include <sys/sysctl.h>
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static void sys_cache_info(int *isize, int *dsize)
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{
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/* There's only a single sysctl for both I/D cache line sizes. */
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int size;
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size_t len = sizeof(size);
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if (!sysctlbyname("machdep.cacheline_size", &size, &len, NULL, 0)) {
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*isize = *dsize = size;
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}
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}
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#else
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/* POSIX */
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static void sys_cache_info(int *isize, int *dsize)
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{
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# ifdef _SC_LEVEL1_ICACHE_LINESIZE
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int tmp_isize = (int) sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
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if (tmp_isize > 0) {
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*isize = tmp_isize;
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}
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# endif
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# ifdef _SC_LEVEL1_DCACHE_LINESIZE
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int tmp_dsize = (int) sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
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if (tmp_dsize > 0) {
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*dsize = tmp_dsize;
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}
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# endif
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}
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#endif /* sys_cache_info */
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/*
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* Architecture (+ OS) specific cache detection mechanisms.
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*/
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#if defined(__powerpc__)
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static bool have_coherent_icache;
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#endif
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#if defined(__aarch64__) && !defined(CONFIG_DARWIN)
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/* Apple does not expose CTR_EL0, so we must use system interfaces. */
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static uint64_t save_ctr_el0;
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static void arch_cache_info(int *isize, int *dsize)
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{
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uint64_t ctr;
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/*
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* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
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* but (at least under Linux) these are marked protected by the
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* kernel. However, CTR_EL0 contains the minimum linesize in the
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* entire hierarchy, and is used by userspace cache flushing.
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*
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* We will also use this value in flush_idcache_range.
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*/
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asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
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save_ctr_el0 = ctr;
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if (*isize == 0 || *dsize == 0) {
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if (*isize == 0) {
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*isize = 4 << (ctr & 0xf);
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}
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if (*dsize == 0) {
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*dsize = 4 << ((ctr >> 16) & 0xf);
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}
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}
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}
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#elif defined(_ARCH_PPC) && defined(__linux__)
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# include "elf.h"
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static void arch_cache_info(int *isize, int *dsize)
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{
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if (*isize == 0) {
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*isize = qemu_getauxval(AT_ICACHEBSIZE);
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}
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if (*dsize == 0) {
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*dsize = qemu_getauxval(AT_DCACHEBSIZE);
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}
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have_coherent_icache = qemu_getauxval(AT_HWCAP) & PPC_FEATURE_ICACHE_SNOOP;
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}
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#else
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static void arch_cache_info(int *isize, int *dsize) { }
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#endif /* arch_cache_info */
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/*
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* ... and if all else fails ...
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*/
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static void fallback_cache_info(int *isize, int *dsize)
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{
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/* If we can only find one of the two, assume they're the same. */
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if (*isize) {
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if (*dsize) {
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/* Success! */
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} else {
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*dsize = *isize;
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}
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} else if (*dsize) {
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*isize = *dsize;
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} else {
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#if defined(_ARCH_PPC)
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/*
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* For PPC, we're going to use the cache sizes computed for
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* flush_idcache_range. Which means that we must use the
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* architecture minimum.
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*/
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*isize = *dsize = 16;
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#else
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/* Otherwise, 64 bytes is not uncommon. */
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*isize = *dsize = 64;
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#endif
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}
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}
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static void __attribute__((constructor)) init_cache_info(void)
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{
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int isize = 0, dsize = 0;
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sys_cache_info(&isize, &dsize);
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arch_cache_info(&isize, &dsize);
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fallback_cache_info(&isize, &dsize);
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assert((isize & (isize - 1)) == 0);
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assert((dsize & (dsize - 1)) == 0);
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qemu_icache_linesize = isize;
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qemu_icache_linesize_log = ctz32(isize);
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qemu_dcache_linesize = dsize;
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qemu_dcache_linesize_log = ctz32(dsize);
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qatomic64_init();
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}
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/*
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* Architecture (+ OS) specific cache flushing mechanisms.
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*/
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
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/* Caches are coherent and do not require flushing; symbol inline. */
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#elif defined(__aarch64__)
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#ifdef CONFIG_DARWIN
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/* Apple does not expose CTR_EL0, so we must use system interfaces. */
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extern void sys_icache_invalidate(void *start, size_t len);
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extern void sys_dcache_flush(void *start, size_t len);
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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sys_dcache_flush((void *)rw, len);
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sys_icache_invalidate((void *)rx, len);
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}
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#else
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/*
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* This is a copy of gcc's __aarch64_sync_cache_range, modified
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* to fit this three-operand interface.
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*/
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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const unsigned CTR_IDC = 1u << 28;
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const unsigned CTR_DIC = 1u << 29;
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const uint64_t ctr_el0 = save_ctr_el0;
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const uintptr_t icache_lsize = qemu_icache_linesize;
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const uintptr_t dcache_lsize = qemu_dcache_linesize;
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uintptr_t p;
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/*
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* If CTR_EL0.IDC is enabled, Data cache clean to the Point of Unification
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* is not required for instruction to data coherence.
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*/
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if (!(ctr_el0 & CTR_IDC)) {
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/*
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* Loop over the address range, clearing one cache line at once.
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* Data cache must be flushed to unification first to make sure
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* the instruction cache fetches the updated data.
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*/
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for (p = rw & -dcache_lsize; p < rw + len; p += dcache_lsize) {
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asm volatile("dc\tcvau, %0" : : "r" (p) : "memory");
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}
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asm volatile("dsb\tish" : : : "memory");
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}
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/*
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* If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point
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* of Unification is not required for instruction to data coherence.
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*/
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if (!(ctr_el0 & CTR_DIC)) {
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for (p = rx & -icache_lsize; p < rx + len; p += icache_lsize) {
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asm volatile("ic\tivau, %0" : : "r"(p) : "memory");
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}
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asm volatile ("dsb\tish" : : : "memory");
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}
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asm volatile("isb" : : : "memory");
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}
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#endif /* CONFIG_DARWIN */
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#elif defined(__mips__)
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#ifdef __OpenBSD__
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#include <machine/sysarch.h>
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#else
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#include <sys/cachectl.h>
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#endif
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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if (rx != rw) {
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cacheflush((void *)rw, len, DCACHE);
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}
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cacheflush((void *)rx, len, ICACHE);
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}
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#elif defined(__powerpc__)
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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uintptr_t p, b, e;
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size_t dsize, isize;
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/*
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* Some processors have coherent caches and support a simplified
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* flushing procedure. See
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* POWER9 UM, 4.6.2.2 Instruction Cache Block Invalidate (icbi)
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* https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
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*/
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if (have_coherent_icache) {
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asm volatile ("sync\n\t"
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"icbi 0,%0\n\t"
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"isync"
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: : "r"(rx) : "memory");
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return;
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}
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dsize = qemu_dcache_linesize;
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isize = qemu_icache_linesize;
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b = rw & ~(dsize - 1);
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e = (rw + len + dsize - 1) & ~(dsize - 1);
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for (p = b; p < e; p += dsize) {
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asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
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}
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asm volatile ("sync" : : : "memory");
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b = rx & ~(isize - 1);
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e = (rx + len + isize - 1) & ~(isize - 1);
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for (p = b; p < e; p += isize) {
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asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
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}
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asm volatile ("sync" : : : "memory");
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asm volatile ("isync" : : : "memory");
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}
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#elif defined(__sparc__)
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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/* No additional data flush to the RW virtual address required. */
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uintptr_t p, end = (rx + len + 7) & -8;
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for (p = rx & -8; p < end; p += 8) {
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__asm__ __volatile__("flush\t%0" : : "r" (p));
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}
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}
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#else
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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if (rw != rx) {
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__builtin___clear_cache((char *)rw, (char *)rw + len);
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}
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__builtin___clear_cache((char *)rx, (char *)rx + len);
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}
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#endif
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