Richard Henderson a0245d91dd target/riscv: Use gen_shift*_per_ol for RVB, RVI ... Most shift instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-14-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-10-22 23:35:47 +10:00
..
insn_trans	target/riscv: Use gen_shift*_per_ol for RVB, RVI	2021-10-22 23:35:47 +10:00
arch_dump.c
bitmanip_helper.c
cpu_bits.h
cpu_helper.c	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	2021-10-22 07:47:51 +10:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	2021-10-22 07:47:51 +10:00
cpu.h	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	2021-10-22 07:47:51 +10:00
csr.c	target/riscv: Add MXL/SXL/UXL to TB_FLAGS	2021-10-22 07:47:51 +10:00
fpu_helper.c
gdbstub.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h
Kconfig
machine.c
meson.build
monitor.c	target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl	2021-10-22 07:47:51 +10:00
op_helper.c
pmp.c
pmp.h
trace-events
trace.h
translate.c	target/riscv: Use gen_shift*_per_ol for RVB, RVI	2021-10-22 23:35:47 +10:00
vector_helper.c