7568b20555
These functions add support for building EPYC mode topology given the smp details like numa nodes, cores, threads and sockets. The new apic id decoding is mostly similar to current apic id decoding except that it adds a new field node_id when numa configured. Removes all the hardcoded values. Subsequent patches will use these functions to build the topology. Following functions are added. apicid_llc_width_epyc apicid_llc_offset_epyc apicid_pkg_offset_epyc apicid_from_topo_ids_epyc x86_topo_ids_from_idx_epyc x86_topo_ids_from_apicid_epyc x86_apicid_from_cpu_idx_epyc The topology details are available in Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. The revision guides are available from the bugzilla Link below. Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger <babu.moger@amd.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <158396721426.58170.2930696192478912976.stgit@naples-babu.amd.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
272 lines
9.4 KiB
C
272 lines
9.4 KiB
C
/*
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* x86 CPU topology data structures and functions
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*
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* Copyright (c) 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_I386_TOPOLOGY_H
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#define HW_I386_TOPOLOGY_H
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/* This file implements the APIC-ID-based CPU topology enumeration logic,
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* documented at the following document:
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* Intel® 64 Architecture Processor Topology Enumeration
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* http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
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*
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* This code should be compatible with AMD's "Extended Method" described at:
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* AMD CPUID Specification (Publication #25481)
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* Section 3: Multiple Core Calcuation
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* as long as:
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* nr_threads is set to 1;
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* OFFSET_IDX is assumed to be 0;
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* CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
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*/
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#include "qemu/bitops.h"
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/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
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*/
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typedef uint32_t apic_id_t;
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typedef struct X86CPUTopoIDs {
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unsigned pkg_id;
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unsigned node_id;
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unsigned die_id;
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unsigned core_id;
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unsigned smt_id;
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} X86CPUTopoIDs;
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typedef struct X86CPUTopoInfo {
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unsigned nodes_per_pkg;
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unsigned dies_per_pkg;
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unsigned cores_per_die;
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unsigned threads_per_core;
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} X86CPUTopoInfo;
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/* Return the bit width needed for 'count' IDs
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*/
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static unsigned apicid_bitwidth_for_count(unsigned count)
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{
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g_assert(count >= 1);
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count -= 1;
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return count ? 32 - clz32(count) : 0;
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}
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/* Bit width of the SMT_ID (thread ID) field on the APIC ID
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*/
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static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
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{
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return apicid_bitwidth_for_count(topo_info->threads_per_core);
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}
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/* Bit width of the Core_ID field
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*/
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static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
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{
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return apicid_bitwidth_for_count(topo_info->cores_per_die);
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}
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/* Bit width of the Die_ID field */
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static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
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{
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return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
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}
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/* Bit width of the node_id field per socket */
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static inline unsigned apicid_node_width_epyc(X86CPUTopoInfo *topo_info)
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{
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return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1));
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}
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/* Bit offset of the Core_ID field
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*/
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static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
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{
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return apicid_smt_width(topo_info);
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}
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/* Bit offset of the Die_ID field */
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static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
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{
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return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
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}
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/* Bit offset of the Pkg_ID (socket ID) field
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*/
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static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
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{
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return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
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}
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#define NODE_ID_OFFSET 3 /* Minimum node_id offset if numa configured */
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/*
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* Bit offset of the node_id field
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*
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* Make sure nodes_per_pkg > 0 if numa configured else zero.
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*/
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static inline unsigned apicid_node_offset_epyc(X86CPUTopoInfo *topo_info)
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{
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unsigned offset = apicid_die_offset(topo_info) +
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apicid_die_width(topo_info);
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if (topo_info->nodes_per_pkg) {
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return MAX(NODE_ID_OFFSET, offset);
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} else {
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return offset;
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}
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}
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/* Bit offset of the Pkg_ID (socket ID) field */
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static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info)
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{
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return apicid_node_offset_epyc(topo_info) +
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apicid_node_width_epyc(topo_info);
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}
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/*
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* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
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*
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* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
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*/
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static inline apic_id_t
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x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info,
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const X86CPUTopoIDs *topo_ids)
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{
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return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) |
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(topo_ids->node_id << apicid_node_offset_epyc(topo_info)) |
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(topo_ids->die_id << apicid_die_offset(topo_info)) |
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(topo_ids->core_id << apicid_core_offset(topo_info)) |
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topo_ids->smt_id;
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}
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static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info,
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unsigned cpu_index,
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X86CPUTopoIDs *topo_ids)
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{
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unsigned nr_nodes = MAX(topo_info->nodes_per_pkg, 1);
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unsigned nr_dies = topo_info->dies_per_pkg;
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unsigned nr_cores = topo_info->cores_per_die;
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unsigned nr_threads = topo_info->threads_per_core;
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unsigned cores_per_node = DIV_ROUND_UP((nr_dies * nr_cores * nr_threads),
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nr_nodes);
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topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
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topo_ids->node_id = (cpu_index / cores_per_node) % nr_nodes;
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topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
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topo_ids->core_id = cpu_index / nr_threads % nr_cores;
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topo_ids->smt_id = cpu_index % nr_threads;
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}
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/*
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* Calculate thread/core/package IDs for a specific topology,
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* based on APIC ID
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*/
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static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid,
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X86CPUTopoInfo *topo_info,
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X86CPUTopoIDs *topo_ids)
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{
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topo_ids->smt_id = apicid &
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~(0xFFFFFFFFUL << apicid_smt_width(topo_info));
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topo_ids->core_id =
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(apicid >> apicid_core_offset(topo_info)) &
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~(0xFFFFFFFFUL << apicid_core_width(topo_info));
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topo_ids->die_id =
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(apicid >> apicid_die_offset(topo_info)) &
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~(0xFFFFFFFFUL << apicid_die_width(topo_info));
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topo_ids->node_id =
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(apicid >> apicid_node_offset_epyc(topo_info)) &
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~(0xFFFFFFFFUL << apicid_node_width_epyc(topo_info));
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topo_ids->pkg_id = apicid >> apicid_pkg_offset_epyc(topo_info);
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}
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/*
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* Make APIC ID for the CPU 'cpu_index'
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*
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* 'cpu_index' is a sequential, contiguous ID for the CPU.
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*/
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static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_info,
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unsigned cpu_index)
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{
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X86CPUTopoIDs topo_ids;
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x86_topo_ids_from_idx_epyc(topo_info, cpu_index, &topo_ids);
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return x86_apicid_from_topo_ids_epyc(topo_info, &topo_ids);
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}
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/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
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*
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* The caller must make sure core_id < nr_cores and smt_id < nr_threads.
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*/
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static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
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const X86CPUTopoIDs *topo_ids)
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{
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return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
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(topo_ids->die_id << apicid_die_offset(topo_info)) |
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(topo_ids->core_id << apicid_core_offset(topo_info)) |
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topo_ids->smt_id;
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}
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/* Calculate thread/core/package IDs for a specific topology,
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* based on (contiguous) CPU index
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*/
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static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
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unsigned cpu_index,
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X86CPUTopoIDs *topo_ids)
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{
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unsigned nr_dies = topo_info->dies_per_pkg;
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unsigned nr_cores = topo_info->cores_per_die;
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unsigned nr_threads = topo_info->threads_per_core;
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topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
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topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
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topo_ids->core_id = cpu_index / nr_threads % nr_cores;
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topo_ids->smt_id = cpu_index % nr_threads;
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}
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/* Calculate thread/core/package IDs for a specific topology,
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* based on APIC ID
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*/
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static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
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X86CPUTopoInfo *topo_info,
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X86CPUTopoIDs *topo_ids)
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{
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topo_ids->smt_id = apicid &
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~(0xFFFFFFFFUL << apicid_smt_width(topo_info));
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topo_ids->core_id =
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(apicid >> apicid_core_offset(topo_info)) &
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~(0xFFFFFFFFUL << apicid_core_width(topo_info));
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topo_ids->die_id =
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(apicid >> apicid_die_offset(topo_info)) &
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~(0xFFFFFFFFUL << apicid_die_width(topo_info));
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topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
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}
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/* Make APIC ID for the CPU 'cpu_index'
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*
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* 'cpu_index' is a sequential, contiguous ID for the CPU.
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*/
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static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
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unsigned cpu_index)
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{
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X86CPUTopoIDs topo_ids;
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x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids);
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return x86_apicid_from_topo_ids(topo_info, &topo_ids);
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}
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#endif /* HW_I386_TOPOLOGY_H */
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