qemu-e2k/target/riscv
Claudio Fontana 7827168471 cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.

Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.

This leaves just a NULL pointer in the cpu.h for the non-TCG builds.

This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-16-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05 10:24:15 -10:00
..
insn_trans riscv: Add semihosting support 2021-01-18 10:05:06 +00:00
cpu_bits.h riscv: Add semihosting support 2021-01-18 10:05:06 +00:00
cpu_helper.c cpu: move cc->transaction_failed to tcg_ops 2021-02-05 10:24:14 -10:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu-param.h target/riscv: Add a virtualised MMU Mode 2020-11-09 15:08:45 -08:00
cpu.c cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
cpu.h target/riscv: Generate the GDB XML file for CSR registers dynamically 2021-01-16 10:57:21 -08:00
csr.c target/riscv: Add CSR name in the CSR function table 2021-01-16 10:57:21 -08:00
fpu_helper.c target/riscv: fpu_helper: Match function defs in HELPER macros 2020-12-17 21:56:44 -08:00
gdbstub.c target/riscv: Generate the GDB XML file for CSR registers dynamically 2021-01-16 10:57:21 -08:00
helper.h target/riscv: fpu_helper: Match function defs in HELPER macros 2020-12-17 21:56:44 -08:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2020-08-25 09:11:35 -07:00
insn32.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2020-08-25 09:11:35 -07:00
instmap.h target/riscv: progressively load the instruction during decode 2020-02-25 20:20:23 +00:00
internals.h target/riscv: Add basic vmstate description of CPU 2020-11-03 07:17:23 -08:00
machine.c target/riscv: Add V extension state description 2020-11-03 07:17:23 -08:00
meson.build target/riscv: Add basic vmstate description of CPU 2020-11-03 07:17:23 -08:00
monitor.c hmp: Pass monitor to mon_get_cpu_env() 2020-11-13 12:45:51 +00:00
op_helper.c target/riscv/pmp: Raise exception if no PMP entry is configured 2021-01-16 10:57:21 -08:00
pmp.c target/riscv/pmp: Raise exception if no PMP entry is configured 2021-01-16 10:57:21 -08:00
pmp.h target/riscv/pmp: Raise exception if no PMP entry is configured 2021-01-16 10:57:21 -08:00
trace-events trace-events: Fix attribution of trace points to source 2020-09-09 17:17:58 +01:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c riscv: Add semihosting support 2021-01-18 10:05:06 +00:00
vector_helper.c softfloat: Implement the full set of comparisons for float16 2020-08-28 10:48:07 -07:00