qemu-e2k/target/sparc
Richard Henderson 2c4f56c9aa target/sparc: Check for invalid cond in gen_compare_reg
Consolidate the test here; drop the "inverted logic".
Fix MOVr and FMOVR, which were missing the invalid test.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-05 12:07:21 -08:00
..
asi.h other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
cpu-feature.h.inc target/sparc: Remove sparcv7 cpu features 2023-10-25 01:01:12 -07:00
cpu-param.h target/sparc: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu-qom.h
cpu.c target/sparc: Remove CC_OP leftovers 2023-11-05 12:03:17 -08:00
cpu.h target/sparc: Remove CC_OP leftovers 2023-11-05 12:03:17 -08:00
fop_helper.c target/sparc: Merge LDFSR, LDXFSR implementations 2023-10-25 01:01:13 -07:00
gdbstub.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
helper.c target/sparc: Implement UDIVX and SDIVX inline 2023-11-05 12:07:10 -08:00
helper.h target/sparc: Implement UDIVX and SDIVX inline 2023-11-05 12:07:10 -08:00
insns.decode target/sparc: Implement UDIV inline 2023-11-05 12:07:17 -08:00
int32_helper.c target/sparc: Remove CC_OP leftovers 2023-11-05 12:03:17 -08:00
int64_helper.c target/sparc: Remove CC_OP leftovers 2023-11-05 12:03:17 -08:00
Kconfig
ldst_helper.c target/sparc: Avoid helper_raise_exception in helper_st_asi 2023-10-25 01:01:12 -07:00
machine.c target/sparc: Split psr and xcc into components 2023-11-05 11:53:13 -08:00
meson.build target/sparc: Remove CC_OP leftovers 2023-11-05 12:03:17 -08:00
mmu_helper.c
monitor.c target/sparc: Handle FPRS correctly on big-endian hosts 2023-07-25 14:42:00 +02:00
trace-events
trace.h
translate.c target/sparc: Check for invalid cond in gen_compare_reg 2023-11-05 12:07:21 -08:00
vis_helper.c target/sparc: Use tcg_gen_vec_{add,sub}* 2023-10-25 01:01:13 -07:00
win_helper.c target/sparc: Remove CC_OP leftovers 2023-11-05 12:03:17 -08:00