Frédéric Pétrot a1a3aac448 target/riscv: separation of bitwise logic and arithmetic helpers ... Introduction of a gen_logic function for bitwise logic to implement instructions in which no propagation of information occurs between bits and use of this function on the bitwise instructions. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-6-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-08 15:46:10 +10:00
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trans_privileged.c.inc
trans_rva.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvb.c.inc	target/riscv: separation of bitwise logic and arithmetic helpers	2022-01-08 15:46:10 +10:00
trans_rvd.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvf.c.inc
trans_rvh.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvi.c.inc	target/riscv: separation of bitwise logic and arithmetic helpers	2022-01-08 15:46:10 +10:00
trans_rvm.c.inc
trans_rvv.c.inc	target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns	2022-01-08 15:46:09 +10:00
trans_rvzfh.c.inc	target/riscv: zfh: implement zfhmin extension	2021-12-20 14:51:36 +10:00