605 lines
16 KiB
C
605 lines
16 KiB
C
/*
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* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPLv2.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/arm/pxa.h"
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#include "hw/sd/sd.h"
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#include "hw/qdev-properties.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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#include "qom/object.h"
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#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
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/* This is reusing the SDBus typedef from SD_BUS */
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DECLARE_INSTANCE_CHECKER(SDBus, PXA2XX_MMCI_BUS,
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TYPE_PXA2XX_MMCI_BUS)
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struct PXA2xxMMCIState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq;
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qemu_irq rx_dma;
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qemu_irq tx_dma;
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qemu_irq inserted;
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qemu_irq readonly;
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BlockBackend *blk;
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SDBus sdbus;
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uint32_t status;
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uint32_t clkrt;
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uint32_t spi;
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uint32_t cmdat;
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uint32_t resp_tout;
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uint32_t read_tout;
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int32_t blklen;
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int32_t numblk;
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uint32_t intmask;
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uint32_t intreq;
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int32_t cmd;
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uint32_t arg;
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int32_t active;
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int32_t bytesleft;
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uint8_t tx_fifo[64];
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uint32_t tx_start;
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uint32_t tx_len;
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uint8_t rx_fifo[32];
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uint32_t rx_start;
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uint32_t rx_len;
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uint16_t resp_fifo[9];
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uint32_t resp_len;
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int32_t cmdreq;
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};
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static bool pxa2xx_mmci_vmstate_validate(void *opaque, int version_id)
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{
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PXA2xxMMCIState *s = opaque;
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return s->tx_start < ARRAY_SIZE(s->tx_fifo)
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&& s->rx_start < ARRAY_SIZE(s->rx_fifo)
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&& s->tx_len <= ARRAY_SIZE(s->tx_fifo)
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&& s->rx_len <= ARRAY_SIZE(s->rx_fifo)
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&& s->resp_len <= ARRAY_SIZE(s->resp_fifo);
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}
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static const VMStateDescription vmstate_pxa2xx_mmci = {
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.name = "pxa2xx-mmci",
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(status, PXA2xxMMCIState),
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VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
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VMSTATE_UINT32(spi, PXA2xxMMCIState),
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VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
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VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
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VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
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VMSTATE_INT32(blklen, PXA2xxMMCIState),
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VMSTATE_INT32(numblk, PXA2xxMMCIState),
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VMSTATE_UINT32(intmask, PXA2xxMMCIState),
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VMSTATE_UINT32(intreq, PXA2xxMMCIState),
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VMSTATE_INT32(cmd, PXA2xxMMCIState),
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VMSTATE_UINT32(arg, PXA2xxMMCIState),
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VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
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VMSTATE_INT32(active, PXA2xxMMCIState),
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VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
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VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
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VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
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VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
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VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
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VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
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VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
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VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
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VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
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VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
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VMSTATE_END_OF_LIST()
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}
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};
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#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
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#define MMC_STAT 0x04 /* MMC Status register */
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#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
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#define MMC_SPI 0x0c /* MMC SPI Mode register */
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#define MMC_CMDAT 0x10 /* MMC Command/Data register */
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#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
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#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
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#define MMC_BLKLEN 0x1c /* MMC Block Length register */
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#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
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#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
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#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
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#define MMC_I_REG 0x2c /* MMC Interrupt Request register */
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#define MMC_CMD 0x30 /* MMC Command register */
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#define MMC_ARGH 0x34 /* MMC Argument High register */
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#define MMC_ARGL 0x38 /* MMC Argument Low register */
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#define MMC_RES 0x3c /* MMC Response FIFO */
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#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
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#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
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#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
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#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
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/* Bitfield masks */
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#define STRPCL_STOP_CLK (1 << 0)
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#define STRPCL_STRT_CLK (1 << 1)
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#define STAT_TOUT_RES (1 << 1)
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#define STAT_CLK_EN (1 << 8)
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#define STAT_DATA_DONE (1 << 11)
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#define STAT_PRG_DONE (1 << 12)
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#define STAT_END_CMDRES (1 << 13)
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#define SPI_SPI_MODE (1 << 0)
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#define CMDAT_RES_TYPE (3 << 0)
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#define CMDAT_DATA_EN (1 << 2)
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#define CMDAT_WR_RD (1 << 3)
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#define CMDAT_DMA_EN (1 << 7)
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#define CMDAT_STOP_TRAN (1 << 10)
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#define INT_DATA_DONE (1 << 0)
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#define INT_PRG_DONE (1 << 1)
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#define INT_END_CMD (1 << 2)
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#define INT_STOP_CMD (1 << 3)
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#define INT_CLK_OFF (1 << 4)
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#define INT_RXFIFO_REQ (1 << 5)
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#define INT_TXFIFO_REQ (1 << 6)
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#define INT_TINT (1 << 7)
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#define INT_DAT_ERR (1 << 8)
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#define INT_RES_ERR (1 << 9)
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#define INT_RD_STALLED (1 << 10)
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#define INT_SDIO_INT (1 << 11)
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#define INT_SDIO_SACK (1 << 12)
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#define PRTBUF_PRT_BUF (1 << 0)
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/* Route internal interrupt lines to the global IC and DMA */
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static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
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{
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uint32_t mask = s->intmask;
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if (s->cmdat & CMDAT_DMA_EN) {
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mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
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qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
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qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
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}
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qemu_set_irq(s->irq, !!(s->intreq & ~mask));
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}
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static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
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{
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if (!s->active)
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return;
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if (s->cmdat & CMDAT_WR_RD) {
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while (s->bytesleft && s->tx_len) {
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sdbus_write_byte(&s->sdbus, s->tx_fifo[s->tx_start++]);
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s->tx_start &= 0x1f;
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s->tx_len --;
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s->bytesleft --;
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}
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if (s->bytesleft)
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s->intreq |= INT_TXFIFO_REQ;
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} else
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while (s->bytesleft && s->rx_len < 32) {
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s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
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sdbus_read_byte(&s->sdbus);
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s->bytesleft --;
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s->intreq |= INT_RXFIFO_REQ;
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}
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if (!s->bytesleft) {
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s->active = 0;
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s->intreq |= INT_DATA_DONE;
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s->status |= STAT_DATA_DONE;
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if (s->cmdat & CMDAT_WR_RD) {
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s->intreq |= INT_PRG_DONE;
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s->status |= STAT_PRG_DONE;
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}
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}
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pxa2xx_mmci_int_update(s);
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}
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static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
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{
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int rsplen, i;
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SDRequest request;
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uint8_t response[16];
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s->active = 1;
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s->rx_len = 0;
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s->tx_len = 0;
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s->cmdreq = 0;
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request.cmd = s->cmd;
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request.arg = s->arg;
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request.crc = 0; /* FIXME */
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rsplen = sdbus_do_command(&s->sdbus, &request, response);
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s->intreq |= INT_END_CMD;
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memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
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switch (s->cmdat & CMDAT_RES_TYPE) {
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#define PXAMMCI_RESP(wd, value0, value1) \
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s->resp_fifo[(wd) + 0] |= (value0); \
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s->resp_fifo[(wd) + 1] |= (value1) << 8;
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case 0: /* No response */
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goto complete;
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case 1: /* R1, R4, R5 or R6 */
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if (rsplen < 4)
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goto timeout;
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goto complete;
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case 2: /* R2 */
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if (rsplen < 16)
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goto timeout;
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goto complete;
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case 3: /* R3 */
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if (rsplen < 4)
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goto timeout;
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goto complete;
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complete:
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for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
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PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
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}
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s->status |= STAT_END_CMDRES;
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if (!(s->cmdat & CMDAT_DATA_EN))
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s->active = 0;
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else
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s->bytesleft = s->numblk * s->blklen;
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s->resp_len = 0;
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break;
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timeout:
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s->active = 0;
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s->status |= STAT_TOUT_RES;
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break;
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}
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pxa2xx_mmci_fifo_update(s);
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}
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static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
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uint32_t ret = 0;
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switch (offset) {
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case MMC_STRPCL:
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break;
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case MMC_STAT:
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ret = s->status;
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break;
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case MMC_CLKRT:
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ret = s->clkrt;
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break;
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case MMC_SPI:
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ret = s->spi;
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break;
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case MMC_CMDAT:
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ret = s->cmdat;
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break;
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case MMC_RESTO:
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ret = s->resp_tout;
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break;
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case MMC_RDTO:
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ret = s->read_tout;
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break;
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case MMC_BLKLEN:
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ret = s->blklen;
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break;
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case MMC_NUMBLK:
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ret = s->numblk;
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break;
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case MMC_PRTBUF:
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break;
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case MMC_I_MASK:
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ret = s->intmask;
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break;
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case MMC_I_REG:
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ret = s->intreq;
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break;
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case MMC_CMD:
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ret = s->cmd | 0x40;
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break;
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case MMC_ARGH:
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ret = s->arg >> 16;
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break;
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case MMC_ARGL:
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ret = s->arg & 0xffff;
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break;
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case MMC_RES:
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ret = (s->resp_len < 9) ? s->resp_fifo[s->resp_len++] : 0;
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break;
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case MMC_RXFIFO:
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while (size-- && s->rx_len) {
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ret |= s->rx_fifo[s->rx_start++] << (size << 3);
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s->rx_start &= 0x1f;
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s->rx_len --;
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}
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s->intreq &= ~INT_RXFIFO_REQ;
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pxa2xx_mmci_fifo_update(s);
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break;
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case MMC_RDWAIT:
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break;
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case MMC_BLKS_REM:
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ret = s->numblk;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: incorrect register 0x%02" HWADDR_PRIx "\n",
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__func__, offset);
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}
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trace_pxa2xx_mmci_read(size, offset, ret);
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return ret;
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}
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static void pxa2xx_mmci_write(void *opaque,
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hwaddr offset, uint64_t value, unsigned size)
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{
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PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
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trace_pxa2xx_mmci_write(size, offset, value);
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switch (offset) {
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case MMC_STRPCL:
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if (value & STRPCL_STRT_CLK) {
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s->status |= STAT_CLK_EN;
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s->intreq &= ~INT_CLK_OFF;
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if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
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s->status &= STAT_CLK_EN;
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pxa2xx_mmci_wakequeues(s);
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}
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}
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if (value & STRPCL_STOP_CLK) {
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s->status &= ~STAT_CLK_EN;
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s->intreq |= INT_CLK_OFF;
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s->active = 0;
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}
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pxa2xx_mmci_int_update(s);
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break;
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case MMC_CLKRT:
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s->clkrt = value & 7;
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break;
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case MMC_SPI:
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s->spi = value & 0xf;
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if (value & SPI_SPI_MODE) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: attempted to use card in SPI mode\n", __func__);
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}
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break;
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case MMC_CMDAT:
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s->cmdat = value & 0x3dff;
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s->active = 0;
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s->cmdreq = 1;
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if (!(value & CMDAT_STOP_TRAN)) {
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s->status &= STAT_CLK_EN;
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if (s->status & STAT_CLK_EN)
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pxa2xx_mmci_wakequeues(s);
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}
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pxa2xx_mmci_int_update(s);
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break;
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case MMC_RESTO:
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s->resp_tout = value & 0x7f;
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break;
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case MMC_RDTO:
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s->read_tout = value & 0xffff;
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break;
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case MMC_BLKLEN:
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s->blklen = value & 0xfff;
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break;
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case MMC_NUMBLK:
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s->numblk = value & 0xffff;
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break;
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case MMC_PRTBUF:
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if (value & PRTBUF_PRT_BUF) {
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s->tx_start ^= 32;
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s->tx_len = 0;
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}
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pxa2xx_mmci_fifo_update(s);
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break;
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case MMC_I_MASK:
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s->intmask = value & 0x1fff;
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pxa2xx_mmci_int_update(s);
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break;
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case MMC_CMD:
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s->cmd = value & 0x3f;
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break;
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case MMC_ARGH:
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s->arg &= 0x0000ffff;
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s->arg |= value << 16;
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break;
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case MMC_ARGL:
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s->arg &= 0xffff0000;
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s->arg |= value & 0x0000ffff;
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break;
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case MMC_TXFIFO:
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while (size-- && s->tx_len < 0x20)
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s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
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(value >> (size << 3)) & 0xff;
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s->intreq &= ~INT_TXFIFO_REQ;
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pxa2xx_mmci_fifo_update(s);
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break;
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case MMC_RDWAIT:
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case MMC_BLKS_REM:
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: incorrect reg 0x%02" HWADDR_PRIx " "
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"(value 0x%08" PRIx64 ")\n", __func__, offset, value);
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}
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}
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static const MemoryRegionOps pxa2xx_mmci_ops = {
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.read = pxa2xx_mmci_read,
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.write = pxa2xx_mmci_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
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hwaddr base,
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qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
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{
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DeviceState *dev;
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SysBusDevice *sbd;
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dev = qdev_new(TYPE_PXA2XX_MMCI);
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sbd = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(sbd, 0, base);
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sysbus_connect_irq(sbd, 0, irq);
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qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
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qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
|
|
sysbus_realize_and_unref(sbd, &error_fatal);
|
|
|
|
return PXA2XX_MMCI(dev);
|
|
}
|
|
|
|
static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
|
|
{
|
|
PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
|
|
|
|
qemu_set_irq(s->inserted, inserted);
|
|
}
|
|
|
|
static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
|
|
{
|
|
PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
|
|
|
|
qemu_set_irq(s->readonly, readonly);
|
|
}
|
|
|
|
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
|
|
qemu_irq coverswitch)
|
|
{
|
|
DeviceState *dev = DEVICE(s);
|
|
|
|
s->readonly = readonly;
|
|
s->inserted = coverswitch;
|
|
|
|
pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
|
|
pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
|
|
}
|
|
|
|
static void pxa2xx_mmci_reset(DeviceState *d)
|
|
{
|
|
PXA2xxMMCIState *s = PXA2XX_MMCI(d);
|
|
|
|
s->status = 0;
|
|
s->clkrt = 0;
|
|
s->spi = 0;
|
|
s->cmdat = 0;
|
|
s->resp_tout = 0;
|
|
s->read_tout = 0;
|
|
s->blklen = 0;
|
|
s->numblk = 0;
|
|
s->intmask = 0;
|
|
s->intreq = 0;
|
|
s->cmd = 0;
|
|
s->arg = 0;
|
|
s->active = 0;
|
|
s->bytesleft = 0;
|
|
s->tx_start = 0;
|
|
s->tx_len = 0;
|
|
s->rx_start = 0;
|
|
s->rx_len = 0;
|
|
s->resp_len = 0;
|
|
s->cmdreq = 0;
|
|
memset(s->tx_fifo, 0, sizeof(s->tx_fifo));
|
|
memset(s->rx_fifo, 0, sizeof(s->rx_fifo));
|
|
memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
|
|
}
|
|
|
|
static void pxa2xx_mmci_instance_init(Object *obj)
|
|
{
|
|
PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
DeviceState *dev = DEVICE(obj);
|
|
|
|
memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
|
|
"pxa2xx-mmci", 0x00100000);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
|
|
qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
|
|
|
|
qbus_init(&s->sdbus, sizeof(s->sdbus),
|
|
TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
|
|
}
|
|
|
|
static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->vmsd = &vmstate_pxa2xx_mmci;
|
|
dc->reset = pxa2xx_mmci_reset;
|
|
}
|
|
|
|
static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SDBusClass *sbc = SD_BUS_CLASS(klass);
|
|
|
|
sbc->set_inserted = pxa2xx_mmci_set_inserted;
|
|
sbc->set_readonly = pxa2xx_mmci_set_readonly;
|
|
}
|
|
|
|
static const TypeInfo pxa2xx_mmci_info = {
|
|
.name = TYPE_PXA2XX_MMCI,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(PXA2xxMMCIState),
|
|
.instance_init = pxa2xx_mmci_instance_init,
|
|
.class_init = pxa2xx_mmci_class_init,
|
|
};
|
|
|
|
static const TypeInfo pxa2xx_mmci_bus_info = {
|
|
.name = TYPE_PXA2XX_MMCI_BUS,
|
|
.parent = TYPE_SD_BUS,
|
|
.instance_size = sizeof(SDBus),
|
|
.class_init = pxa2xx_mmci_bus_class_init,
|
|
};
|
|
|
|
static void pxa2xx_mmci_register_types(void)
|
|
{
|
|
type_register_static(&pxa2xx_mmci_info);
|
|
type_register_static(&pxa2xx_mmci_bus_info);
|
|
}
|
|
|
|
type_init(pxa2xx_mmci_register_types)
|