a30bfaa7bd
Split host_signal_pc and host_signal_write out of user-exec.c. Drop the *BSD code, to be re-created under bsd-user/ later. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
875 lines
26 KiB
C
875 lines
26 KiB
C
/*
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* User emulator execution
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/core/tcg-cpu-ops.h"
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#include "disas/disas.h"
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#include "exec/exec-all.h"
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#include "tcg/tcg.h"
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#include "qemu/bitops.h"
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#include "exec/cpu_ldst.h"
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#include "exec/translate-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/atomic128.h"
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#include "trace/trace-root.h"
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#include "internal.h"
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__thread uintptr_t helper_retaddr;
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//#define DEBUG_SIGNAL
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/*
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* Adjust the pc to pass to cpu_restore_state; return the memop type.
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*/
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MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write)
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{
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switch (helper_retaddr) {
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default:
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/*
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* Fault during host memory operation within a helper function.
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* The helper's host return address, saved here, gives us a
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* pointer into the generated code that will unwind to the
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* correct guest pc.
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*/
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*pc = helper_retaddr;
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break;
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case 0:
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/*
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* Fault during host memory operation within generated code.
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* (Or, a unrelated bug within qemu, but we can't tell from here).
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*
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* We take the host pc from the signal frame. However, we cannot
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* use that value directly. Within cpu_restore_state_from_tb, we
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* assume PC comes from GETPC(), as used by the helper functions,
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* so we adjust the address by -GETPC_ADJ to form an address that
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* is within the call insn, so that the address does not accidentally
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* match the beginning of the next guest insn. However, when the
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* pc comes from the signal frame it points to the actual faulting
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* host memory insn and not the return from a call insn.
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*
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* Therefore, adjust to compensate for what will be done later
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* by cpu_restore_state_from_tb.
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*/
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*pc += GETPC_ADJ;
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break;
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case 1:
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/*
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* Fault during host read for translation, or loosely, "execution".
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*
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* The guest pc is already pointing to the start of the TB for which
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* code is being generated. If the guest translator manages the
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* page crossings correctly, this is exactly the correct address
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* (and if the translator doesn't handle page boundaries correctly
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* there's little we can do about that here). Therefore, do not
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* trigger the unwinder.
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*
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* Like tb_gen_code, release the memory lock before cpu_loop_exit.
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*/
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mmap_unlock();
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*pc = 0;
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return MMU_INST_FETCH;
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}
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return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
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}
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/**
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* handle_sigsegv_accerr_write:
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* @cpu: the cpu context
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* @old_set: the sigset_t from the signal ucontext_t
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* @host_pc: the host pc, adjusted for the signal
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* @guest_addr: the guest address of the fault
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*
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* Return true if the write fault has been handled, and should be re-tried.
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*
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* Note that it is important that we don't call page_unprotect() unless
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* this is really a "write to nonwriteable page" fault, because
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* page_unprotect() assumes that if it is called for an access to
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* a page that's writeable this means we had two threads racing and
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* another thread got there first and already made the page writeable;
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* so we will retry the access. If we were to call page_unprotect()
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* for some other kind of fault that should really be passed to the
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* guest, we'd end up in an infinite loop of retrying the faulting access.
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*/
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bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
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uintptr_t host_pc, abi_ptr guest_addr)
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{
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switch (page_unprotect(guest_addr, host_pc)) {
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case 0:
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/*
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* Fault not caused by a page marked unwritable to protect
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* cached translations, must be the guest binary's problem.
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*/
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return false;
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case 1:
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/*
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* Fault caused by protection of cached translation; TBs
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* invalidated, so resume execution.
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*/
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return true;
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case 2:
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/*
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* Fault caused by protection of cached translation, and the
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* currently executing TB was modified and must be exited immediately.
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*/
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sigprocmask(SIG_SETMASK, old_set, NULL);
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cpu_loop_exit_noexc(cpu);
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/* NORETURN */
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default:
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g_assert_not_reached();
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}
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}
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/*
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* 'pc' is the host PC at which the exception was raised.
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* 'address' is the effective address of the memory exception.
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* 'is_write' is 1 if a write caused the exception and otherwise 0.
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* 'old_set' is the signal set which should be restored.
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*/
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static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
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int is_write, sigset_t *old_set)
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{
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CPUState *cpu = current_cpu;
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CPUClass *cc;
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unsigned long host_addr = (unsigned long)info->si_addr;
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MMUAccessType access_type = adjust_signal_pc(&pc, is_write);
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abi_ptr guest_addr;
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/* For synchronous signals we expect to be coming from the vCPU
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* thread (so current_cpu should be valid) and either from running
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* code or during translation which can fault as we cross pages.
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*
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* If neither is true then something has gone wrong and we should
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* abort rather than try and restart the vCPU execution.
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*/
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if (!cpu || !cpu->running) {
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printf("qemu:%s received signal outside vCPU context @ pc=0x%"
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PRIxPTR "\n", __func__, pc);
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abort();
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}
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#if defined(DEBUG_SIGNAL)
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
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pc, host_addr, is_write, *(unsigned long *)old_set);
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#endif
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/* Convert forcefully to guest address space, invalid addresses
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are still valid segv ones */
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guest_addr = h2g_nocheck(host_addr);
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/* XXX: locking issue */
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if (is_write &&
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info->si_signo == SIGSEGV &&
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info->si_code == SEGV_ACCERR &&
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h2g_valid(host_addr) &&
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handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) {
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return 1;
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}
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/*
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* There is no way the target can handle this other than raising
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* an exception. Undo signal and retaddr state prior to longjmp.
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*/
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sigprocmask(SIG_SETMASK, old_set, NULL);
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cc = CPU_GET_CLASS(cpu);
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cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type,
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MMU_USER_IDX, false, pc);
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g_assert_not_reached();
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}
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static int probe_access_internal(CPUArchState *env, target_ulong addr,
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int fault_size, MMUAccessType access_type,
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bool nonfault, uintptr_t ra)
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{
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int flags;
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switch (access_type) {
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case MMU_DATA_STORE:
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flags = PAGE_WRITE;
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break;
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case MMU_DATA_LOAD:
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flags = PAGE_READ;
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break;
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case MMU_INST_FETCH:
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flags = PAGE_EXEC;
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break;
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default:
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g_assert_not_reached();
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}
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if (!guest_addr_valid_untagged(addr) ||
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page_check_range(addr, 1, flags) < 0) {
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if (nonfault) {
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return TLB_INVALID_MASK;
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} else {
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CPUState *cpu = env_cpu(env);
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CPUClass *cc = CPU_GET_CLASS(cpu);
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cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type,
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MMU_USER_IDX, false, ra);
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g_assert_not_reached();
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}
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}
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return 0;
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}
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int probe_access_flags(CPUArchState *env, target_ulong addr,
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MMUAccessType access_type, int mmu_idx,
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bool nonfault, void **phost, uintptr_t ra)
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{
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int flags;
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flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra);
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*phost = flags ? NULL : g2h(env_cpu(env), addr);
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return flags;
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}
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void *probe_access(CPUArchState *env, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t ra)
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{
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int flags;
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g_assert(-(addr | TARGET_PAGE_MASK) >= size);
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flags = probe_access_internal(env, addr, size, access_type, false, ra);
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g_assert(flags == 0);
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return size ? g2h(env_cpu(env), addr) : NULL;
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}
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#if defined(__aarch64__)
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#if defined(__NetBSD__)
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#include <ucontext.h>
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#include <sys/siginfo.h>
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int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
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{
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ucontext_t *uc = puc;
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siginfo_t *si = pinfo;
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unsigned long pc;
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int is_write;
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uint32_t esr;
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pc = uc->uc_mcontext.__gregs[_REG_PC];
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esr = si->si_trap;
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/*
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* siginfo_t::si_trap is the ESR value, for data aborts ESR.EC
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* is 0b10010x: then bit 6 is the WnR bit
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*/
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is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
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return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask);
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}
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#else
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#ifndef ESR_MAGIC
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/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
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#define ESR_MAGIC 0x45535201
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struct esr_context {
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struct _aarch64_ctx head;
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uint64_t esr;
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};
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#endif
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static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)
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{
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return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
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}
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static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
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{
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return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
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}
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int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
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{
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siginfo_t *info = pinfo;
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ucontext_t *uc = puc;
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uintptr_t pc = uc->uc_mcontext.pc;
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bool is_write;
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struct _aarch64_ctx *hdr;
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struct esr_context const *esrctx = NULL;
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/* Find the esr_context, which has the WnR bit in it */
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for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
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if (hdr->magic == ESR_MAGIC) {
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esrctx = (struct esr_context const *)hdr;
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break;
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}
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}
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if (esrctx) {
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/* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
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uint64_t esr = esrctx->esr;
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is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
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} else {
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/*
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* Fall back to parsing instructions; will only be needed
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* for really ancient (pre-3.16) kernels.
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*/
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uint32_t insn = *(uint32_t *)pc;
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is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
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|| (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
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|| (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
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|| (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
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|| (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
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|| (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
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|| (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
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/* Ignore bits 10, 11 & 21, controlling indexing. */
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|| (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
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|| (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
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/* Ignore bits 23 & 24, controlling indexing. */
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|| (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
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}
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return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
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}
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#endif
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#elif defined(__s390__)
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int cpu_signal_handler(int host_signum, void *pinfo,
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void *puc)
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{
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siginfo_t *info = pinfo;
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ucontext_t *uc = puc;
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unsigned long pc;
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uint16_t *pinsn;
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int is_write = 0;
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pc = uc->uc_mcontext.psw.addr;
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/*
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* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
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* of the normal 2 arguments. The 4th argument contains the "Translation-
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* Exception Identification for DAT Exceptions" from the hardware (aka
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* "int_parm_long"), which does in fact contain the is_write value.
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* The rt signal handler, as far as I can tell, does not give this value
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* at all. Not that we could get to it from here even if it were.
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* So fall back to parsing instructions. Treat read-modify-write ones as
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* writes, which is not fully correct, but for tracking self-modifying code
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* this is better than treating them as reads. Checking si_addr page flags
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* might be a viable improvement, albeit a racy one.
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*/
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/* ??? This is not even close to complete. */
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pinsn = (uint16_t *)pc;
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switch (pinsn[0] >> 8) {
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case 0x50: /* ST */
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case 0x42: /* STC */
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case 0x40: /* STH */
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case 0xba: /* CS */
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case 0xbb: /* CDS */
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is_write = 1;
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break;
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case 0xc4: /* RIL format insns */
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switch (pinsn[0] & 0xf) {
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case 0xf: /* STRL */
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case 0xb: /* STGRL */
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case 0x7: /* STHRL */
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is_write = 1;
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}
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break;
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case 0xc8: /* SSF format insns */
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switch (pinsn[0] & 0xf) {
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case 0x2: /* CSST */
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is_write = 1;
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}
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break;
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case 0xe3: /* RXY format insns */
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switch (pinsn[2] & 0xff) {
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case 0x50: /* STY */
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case 0x24: /* STG */
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case 0x72: /* STCY */
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case 0x70: /* STHY */
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case 0x8e: /* STPQ */
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case 0x3f: /* STRVH */
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case 0x3e: /* STRV */
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case 0x2f: /* STRVG */
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is_write = 1;
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}
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break;
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case 0xeb: /* RSY format insns */
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switch (pinsn[2] & 0xff) {
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case 0x14: /* CSY */
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case 0x30: /* CSG */
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case 0x31: /* CDSY */
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case 0x3e: /* CDSG */
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case 0xe4: /* LANG */
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case 0xe6: /* LAOG */
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case 0xe7: /* LAXG */
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case 0xe8: /* LAAG */
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case 0xea: /* LAALG */
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case 0xf4: /* LAN */
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case 0xf6: /* LAO */
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case 0xf7: /* LAX */
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case 0xfa: /* LAAL */
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case 0xf8: /* LAA */
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is_write = 1;
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}
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break;
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}
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return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
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}
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#elif defined(__mips__)
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#if defined(__misp16) || defined(__mips_micromips)
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#error "Unsupported encoding"
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#endif
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int cpu_signal_handler(int host_signum, void *pinfo,
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void *puc)
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{
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siginfo_t *info = pinfo;
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ucontext_t *uc = puc;
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uintptr_t pc = uc->uc_mcontext.pc;
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uint32_t insn = *(uint32_t *)pc;
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int is_write = 0;
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/* Detect all store instructions at program counter. */
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switch((insn >> 26) & 077) {
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case 050: /* SB */
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case 051: /* SH */
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case 052: /* SWL */
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case 053: /* SW */
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case 054: /* SDL */
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case 055: /* SDR */
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case 056: /* SWR */
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case 070: /* SC */
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case 071: /* SWC1 */
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case 074: /* SCD */
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case 075: /* SDC1 */
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case 077: /* SD */
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#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
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case 072: /* SWC2 */
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case 076: /* SDC2 */
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#endif
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is_write = 1;
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break;
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case 023: /* COP1X */
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/* Required in all versions of MIPS64 since
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MIPS64r1 and subsequent versions of MIPS32r2. */
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switch (insn & 077) {
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case 010: /* SWXC1 */
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case 011: /* SDXC1 */
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case 015: /* SUXC1 */
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is_write = 1;
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}
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break;
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}
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return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
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}
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#elif defined(__riscv)
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|
int cpu_signal_handler(int host_signum, void *pinfo,
|
|
void *puc)
|
|
{
|
|
siginfo_t *info = pinfo;
|
|
ucontext_t *uc = puc;
|
|
greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
|
|
uint32_t insn = *(uint32_t *)pc;
|
|
int is_write = 0;
|
|
|
|
/* Detect store by reading the instruction at the program
|
|
counter. Note: we currently only generate 32-bit
|
|
instructions so we thus only detect 32-bit stores */
|
|
switch (((insn >> 0) & 0b11)) {
|
|
case 3:
|
|
switch (((insn >> 2) & 0b11111)) {
|
|
case 8:
|
|
switch (((insn >> 12) & 0b111)) {
|
|
case 0: /* sb */
|
|
case 1: /* sh */
|
|
case 2: /* sw */
|
|
case 3: /* sd */
|
|
case 4: /* sq */
|
|
is_write = 1;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 9:
|
|
switch (((insn >> 12) & 0b111)) {
|
|
case 2: /* fsw */
|
|
case 3: /* fsd */
|
|
case 4: /* fsq */
|
|
is_write = 1;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Check for compressed instructions */
|
|
switch (((insn >> 13) & 0b111)) {
|
|
case 7:
|
|
switch (insn & 0b11) {
|
|
case 0: /*c.sd */
|
|
case 2: /* c.sdsp */
|
|
is_write = 1;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
case 6:
|
|
switch (insn & 0b11) {
|
|
case 0: /* c.sw */
|
|
case 3: /* c.swsp */
|
|
is_write = 1;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
|
|
}
|
|
#endif
|
|
|
|
/* The softmmu versions of these helpers are in cputlb.c. */
|
|
|
|
/*
|
|
* Verify that we have passed the correct MemOp to the correct function.
|
|
*
|
|
* We could present one function to target code, and dispatch based on
|
|
* the MemOp, but so far we have worked hard to avoid an indirect function
|
|
* call along the memory path.
|
|
*/
|
|
static void validate_memop(MemOpIdx oi, MemOp expected)
|
|
{
|
|
#ifdef CONFIG_DEBUG_TCG
|
|
MemOp have = get_memop(oi) & (MO_SIZE | MO_BSWAP);
|
|
assert(have == expected);
|
|
#endif
|
|
}
|
|
|
|
static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr,
|
|
MemOpIdx oi, uintptr_t ra, MMUAccessType type)
|
|
{
|
|
void *ret;
|
|
|
|
/* TODO: Enforce guest required alignment. */
|
|
|
|
ret = g2h(env_cpu(env), addr);
|
|
set_helper_retaddr(ra);
|
|
return ret;
|
|
}
|
|
|
|
uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
uint8_t ret;
|
|
|
|
validate_memop(oi, MO_UB);
|
|
trace_guest_ld_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
|
|
ret = ldub_p(haddr);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
|
|
return ret;
|
|
}
|
|
|
|
uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
uint16_t ret;
|
|
|
|
validate_memop(oi, MO_BEUW);
|
|
trace_guest_ld_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
|
|
ret = lduw_be_p(haddr);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
|
|
return ret;
|
|
}
|
|
|
|
uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
uint32_t ret;
|
|
|
|
validate_memop(oi, MO_BEUL);
|
|
trace_guest_ld_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
|
|
ret = ldl_be_p(haddr);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
|
|
return ret;
|
|
}
|
|
|
|
uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
uint64_t ret;
|
|
|
|
validate_memop(oi, MO_BEQ);
|
|
trace_guest_ld_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
|
|
ret = ldq_be_p(haddr);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
|
|
return ret;
|
|
}
|
|
|
|
uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
uint16_t ret;
|
|
|
|
validate_memop(oi, MO_LEUW);
|
|
trace_guest_ld_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
|
|
ret = lduw_le_p(haddr);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
|
|
return ret;
|
|
}
|
|
|
|
uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
uint32_t ret;
|
|
|
|
validate_memop(oi, MO_LEUL);
|
|
trace_guest_ld_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
|
|
ret = ldl_le_p(haddr);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
|
|
return ret;
|
|
}
|
|
|
|
uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
uint64_t ret;
|
|
|
|
validate_memop(oi, MO_LEQ);
|
|
trace_guest_ld_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
|
|
ret = ldq_le_p(haddr);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
|
|
return ret;
|
|
}
|
|
|
|
void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
|
|
validate_memop(oi, MO_UB);
|
|
trace_guest_st_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
|
|
stb_p(haddr, val);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
|
|
}
|
|
|
|
void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr, uint16_t val,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
|
|
validate_memop(oi, MO_BEUW);
|
|
trace_guest_st_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
|
|
stw_be_p(haddr, val);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
|
|
}
|
|
|
|
void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, uint32_t val,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
|
|
validate_memop(oi, MO_BEUL);
|
|
trace_guest_st_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
|
|
stl_be_p(haddr, val);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
|
|
}
|
|
|
|
void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, uint64_t val,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
|
|
validate_memop(oi, MO_BEQ);
|
|
trace_guest_st_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
|
|
stq_be_p(haddr, val);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
|
|
}
|
|
|
|
void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr, uint16_t val,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
|
|
validate_memop(oi, MO_LEUW);
|
|
trace_guest_st_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
|
|
stw_le_p(haddr, val);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
|
|
}
|
|
|
|
void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr, uint32_t val,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
|
|
validate_memop(oi, MO_LEUL);
|
|
trace_guest_st_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
|
|
stl_le_p(haddr, val);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
|
|
}
|
|
|
|
void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, uint64_t val,
|
|
MemOpIdx oi, uintptr_t ra)
|
|
{
|
|
void *haddr;
|
|
|
|
validate_memop(oi, MO_LEQ);
|
|
trace_guest_st_before_exec(env_cpu(env), addr, oi);
|
|
haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
|
|
stq_le_p(haddr, val);
|
|
clear_helper_retaddr();
|
|
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
|
|
}
|
|
|
|
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr)
|
|
{
|
|
uint32_t ret;
|
|
|
|
set_helper_retaddr(1);
|
|
ret = ldub_p(g2h_untagged(ptr));
|
|
clear_helper_retaddr();
|
|
return ret;
|
|
}
|
|
|
|
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr ptr)
|
|
{
|
|
uint32_t ret;
|
|
|
|
set_helper_retaddr(1);
|
|
ret = lduw_p(g2h_untagged(ptr));
|
|
clear_helper_retaddr();
|
|
return ret;
|
|
}
|
|
|
|
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr ptr)
|
|
{
|
|
uint32_t ret;
|
|
|
|
set_helper_retaddr(1);
|
|
ret = ldl_p(g2h_untagged(ptr));
|
|
clear_helper_retaddr();
|
|
return ret;
|
|
}
|
|
|
|
uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr)
|
|
{
|
|
uint64_t ret;
|
|
|
|
set_helper_retaddr(1);
|
|
ret = ldq_p(g2h_untagged(ptr));
|
|
clear_helper_retaddr();
|
|
return ret;
|
|
}
|
|
|
|
#include "ldst_common.c.inc"
|
|
|
|
/*
|
|
* Do not allow unaligned operations to proceed. Return the host address.
|
|
*
|
|
* @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
|
|
*/
|
|
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
|
|
MemOpIdx oi, int size, int prot,
|
|
uintptr_t retaddr)
|
|
{
|
|
/* Enforce qemu required alignment. */
|
|
if (unlikely(addr & (size - 1))) {
|
|
cpu_loop_exit_atomic(env_cpu(env), retaddr);
|
|
}
|
|
void *ret = g2h(env_cpu(env), addr);
|
|
set_helper_retaddr(retaddr);
|
|
return ret;
|
|
}
|
|
|
|
#include "atomic_common.c.inc"
|
|
|
|
/*
|
|
* First set of functions passes in OI and RETADDR.
|
|
* This makes them callable from other helpers.
|
|
*/
|
|
|
|
#define ATOMIC_NAME(X) \
|
|
glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu)
|
|
#define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0)
|
|
#define ATOMIC_MMU_IDX MMU_USER_IDX
|
|
|
|
#define DATA_SIZE 1
|
|
#include "atomic_template.h"
|
|
|
|
#define DATA_SIZE 2
|
|
#include "atomic_template.h"
|
|
|
|
#define DATA_SIZE 4
|
|
#include "atomic_template.h"
|
|
|
|
#ifdef CONFIG_ATOMIC64
|
|
#define DATA_SIZE 8
|
|
#include "atomic_template.h"
|
|
#endif
|
|
|
|
#if HAVE_ATOMIC128 || HAVE_CMPXCHG128
|
|
#define DATA_SIZE 16
|
|
#include "atomic_template.h"
|
|
#endif
|