qemu-e2k/disas
Rahul Pathak 513eb437ae target/riscv: Remove sideleg and sedeleg
sideleg and sedeleg csrs are not part of riscv isa spec
anymore, these csrs were part of N extension which
is removed from the riscv isa specification.

These commits removed all traces of these csrs from
riscv spec (https://github.com/riscv/riscv-isa-manual) -

commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)")
commit b6cade07034d ("Remove N extension chapter for now")

Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-27 07:04:38 +10:00
..
alpha.c
capstone.c disas: Push const down through host disassembly 2021-01-07 05:09:42 -10:00
cris.c
hexagon.c Hexagon (disas/hexagon.c) fix memory leak for early exit cases 2021-08-12 09:06:05 -05:00
hppa.c disas/: fix some comment spelling errors 2020-09-17 20:40:08 +02:00
m68k.c disas/: fix some comment spelling errors 2020-09-17 20:40:08 +02:00
meson.build disas: Remove libvixl disassembler 2022-07-05 10:15:49 +02:00
microblaze.c
mips.c
nanomips.cpp include/disas/dis-asm.h: Handle being included outside 'extern "C"' 2021-05-10 17:21:54 +01:00
nanomips.h
nios2.c disas/nios2: Simplify endianess conversion 2021-10-22 18:07:30 +02:00
riscv.c target/riscv: Remove sideleg and sedeleg 2022-09-27 07:04:38 +10:00
sh4.c
sparc.c
xtensa.c