430 lines
15 KiB
C
430 lines
15 KiB
C
#include "qemu/osdep.h"
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#include "qemu.h"
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#include "tcg/tcg-op.h"
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#include "exec/log.h"
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#include "exec/translator.h"
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#include "translate.h"
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static void gen_cs0(DisasContext *dc)
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{
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typedef enum {
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NOTHING,
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IBRANCH,
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PREF,
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PUTTSD,
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DONE,
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HRET,
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GLAUNCH,
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DISP,
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SDISP,
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GETTSD,
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LDISP,
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RETURN
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} cs0_type;
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static cs0_type cs0_ops[4][4] = {
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{IBRANCH, PREF, PUTTSD, DONE},
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{DISP, NOTHING, SDISP, GETTSD},
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{DISP, LDISP, SDISP, GETTSD},
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{DISP, NOTHING, SDISP, RETURN}
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};
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const UnpackedBundle *bundle = &dc->bundle;
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uint32_t cs0 = bundle->cs0;
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unsigned int ctpr = (cs0 & 0xc0000000) >> 30;
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unsigned int ctp_opc = (cs0 & 0x30000000) >> 28;
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unsigned int param_type = (cs0 & 0x00000007);
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cs0_type type = cs0_ops[ctpr][ctp_opc];
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if (type == RETURN && param_type == 1) {
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type = GETTSD;
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} else if (type == DONE) {
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if (param_type == 3) {
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type = HRET;
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} else if (param_type == 4) {
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type = GLAUNCH;
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}
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}
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if (type == IBRANCH || type == DONE || type == HRET || type == GLAUNCH) {
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/* IBRANCH, DONE, HRET and GLAUNCH are special because they require SS
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to be properly encoded. */
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if (! bundle->ss_present
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/* SS.ctop should be equal to zero for IBRANCH, DONE, HRET and
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GLAUNCH (see C.17.1.1, note that they don't mention the latter two
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instructions there which is probably an omission ). */
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|| (bundle->ss & 0x00000c00))
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{
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// TODO: invalid
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abort();
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}
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/* Don't output either of the aforementioned instructions under "never"
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condition. Don't disassemble CS0 being a part of HCALL. Unlike ldis
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HCALL is currently disassembled on behalf of CS1. */
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else if ((bundle->ss & 0x1ff)
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&& !(bundle->cs1_present
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/* CS1.opc == CALL */
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&& (bundle->cs1 & 0xf0000000) >> 28 == 5
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/* CS1.param.ctopc == HCALL */
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&& (bundle->cs1 & 0x380) >> 7 == 2))
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{
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if (type == IBRANCH) {
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/* C0F2 has `disp' field. In `C0F1' it's called `param'. Is this
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the only difference between these two formats? Funnily enough,
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DONE is also C0F2 and thus has `disp', though it obviously
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makes no sense for it. */
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unsigned int disp = (cs0 & 0x0fffffff);
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/* Calculate a signed displacement in bytes. */
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int sdisp = ((int) (disp << 4)) >> 1;
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target_ulong tgt = dc->pc + sdisp;
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TCGv dest = e2k_get_temp(dc);
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tcg_gen_movi_tl(dest, tgt);
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dc->jmp.dest = dest;
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}
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}
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} else {
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/* Note that according to Table B.4.1 it's possible to obtain
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` gettsd %ctpr{1,2} with an invalid value for CS0.param.type. */
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if (type == GETTSD && param_type != 1) {
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// invalid
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abort();
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}
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if (type == DISP
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|| type == SDISP
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|| type == LDISP
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/* Note that RETURN is said to be COPF1. I can't understand what its
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`CS0.param' is needed for: all of the bits except the three
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lowermost ones are undefined, while the latter also known as "type"
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field should be filled in with zeroes. */
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|| type == RETURN
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/* GETTSD has as meaningless `CS0.param' as RETURN. The only
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difference is that its `CS0.param.type' should be equal to `1'. I
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wonder if I should check for that and output something like
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"invalid gettsd" if this turns out not to be the case . . . */
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|| type == GETTSD)
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{
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// ctpr
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}
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if (type == SDISP) {
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// my_printf (", 0x%x", cs0 & 0x1f);
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} else if (type == DISP
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|| type == LDISP
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|| type == PUTTSD)
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{
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// unsigned int disp = (cs0 & 0x0fffffff);
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// int sgnd_disp = ((int) (disp << 4)) >> 1;
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/* PUTTSD obviously doesn't take %ctpr{j} parameter. TODO: beware of
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an optional predicate which may control its execution which is
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encoded via `SS.ctcond.psrc' and `SS.ts_opc == PUTTSDC{P,N}' in
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case of `SS.type == 1' (see C.21.4). I wonder if `ct %ctpr<j>'
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encoded in `SS.ctop' under the same `SS.ctcond' takes an effect in
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such a case. */
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// my_printf ("%s0x%llx", type == PUTTSD ? "" : ", ",
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/* FIXME: this way I ensure that it'll work correctly
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both on 32 and 64-bit hosts. */
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// (unsigned long long) (instr_addr + sgnd_disp));
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}
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if (type == PREF) {
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// unsigned int pdisp = (bundle->cs0 & 0x0ffffff0) >> 4;
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// unsigned int ipd = (bundle->cs0 & 0x00000008) >> 3;
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// unsigned int prefr = bundle->cs0 & 0x00000007;
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}
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}
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}
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static void gen_cs1(DisasContext *dc)
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{
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enum {
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SETR0,
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SETR1,
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SETEI,
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WAIT,
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SETBR,
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CALL,
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MAS_OPC,
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FLUSHR,
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BG
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};
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const UnpackedBundle *bundle = &dc->bundle;
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unsigned int cs1 = bundle->cs1;
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unsigned int opc = (cs1 & 0xf0000000) >> 28;
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if (opc == SETR0 || opc == SETR1 || opc == SETBR) {
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unsigned int setbp = (cs1 & 0x08000000) >> 27;
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unsigned int setbn = (cs1 & 0x04000000) >> 26;
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/* Try to follow the same order of these instructions as in LDIS.
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Presumably `vfrpsz' should come first, while `setbp' should be placed
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between `setwd' and `setbn', but this is to be verified. I don't have
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a binary with these commands by hand right now. */
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if (opc == SETR1) {
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if (! bundle->lts_present[0]) {
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// my_printf ("<bogus vfrpsz>");
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} else {
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/* Find out if VFRPSZ is always encoded together with SETWD. This
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seems to be the case even if no SETWD has been explicitly
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specified. */
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// unsigned int rpsz = (bundle->lts[0] & 0x0001f000) >> 12;
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// my_printf ("vfrpsz rpsz = 0x%x", rpsz);
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}
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}
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// FIXME: Should windowing registers be precomputed or not?
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if (opc == SETR0 || opc == SETR1) {
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if (! bundle->lts_present[0]) {
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// TODO: <bogus setwd>
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abort();
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} else {
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uint32_t lts0 = bundle->lts[0];
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tcg_gen_movi_i32(e2k_cs.wsz, GET_FIELD(lts0, 5, 11) * 2);
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tcg_gen_movi_i32(e2k_cs.nfx, GET_BIT(lts0, 4));
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if (dc->version >= 3) {
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tcg_gen_movi_i32(e2k_cs.dbl, GET_BIT(lts0, 3));
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}
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}
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}
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if (setbn) {
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unsigned int rcur = (cs1 & 0x0003f000) >> 12;
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unsigned int rsz = (cs1 & 0x00000fc0) >> 6;
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unsigned int rbs = cs1 & 0x0000003f;
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tcg_gen_movi_i32(e2k_cs.rcur, rcur * 2);
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tcg_gen_movi_i32(e2k_cs.rsz, rsz * 2 + 2);
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tcg_gen_movi_i32(e2k_cs.rbs, rbs * 2);
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}
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if (setbp) {
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unsigned int psz = (cs1 & 0x007c0000) >> 18;
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tcg_gen_movi_i32(e2k_cs.psz, psz);
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}
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} else if (opc == SETEI) {
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/* Verify that CS1.param.sft = CS1.param[27] is equal to zero as required
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in C.14.3. */
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unsigned int sft = (cs1 & 0x08000000) >> 27;
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// unsigned int eir = (cs1 & 0x000000ff);
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if (sft) {
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// my_printf ("%s", mcpu >= 2 ? "setsft" : "unimp");
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} else {
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// my_printf ("setei 0x%x", eir);
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}
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} else if (opc == WAIT) {
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// unsigned int ma_c = (cs1 & 0x00000020) >> 5;
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// unsigned int fl_c = (cs1 & 0x00000010) >> 4;
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unsigned int ld_c = (cs1 & 0x00000008) >> 3;
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unsigned int st_c = (cs1 & 0x00000004) >> 2;
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// unsigned int all_e = (cs1 & 0x00000002) >> 1;
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// unsigned int all_c = cs1 & 0x00000001;
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if (dc->version >= 5) {
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/* `sa{l,s}' fields are `elbrus-v5'-specific. Each of them makes sense
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only in the presence of `{ld,st}_c == 1' respectively. */
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if (ld_c) {
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// unsigned int sal = (cs1 & 0x00000100) >> 8;
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// my_printf ("sal = %d, ", sal);
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}
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if (st_c) {
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// unsigned int sas = (cs1 & 0x00000080) >> 7;
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// my_printf ("sas = %d, ", sas);
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}
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}
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if (dc->version >= 2) {
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/* `trap' field was introduced starting from `elbrus-v2'. */
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// unsigned int trap = (cs1 & 0x00000040) >> 6;
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// my_printf ("trap = %d, ", trap);
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}
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// my_printf ("ma_c = %d, fl_c = %d, ld_c = %d, st_c = %d, all_e = %d, "
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// "all_c = %d", ma_c, fl_c, ld_c, st_c, all_e, all_c);
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} else if (opc == CALL) {
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unsigned int ctop = (bundle->ss & 0x00000c00) >> 10;
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/* In C.17.4 it's said that other bits in CS1.param except for the
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seven lowermost ones are ignored. */
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// unsigned int wbs = cs1 & 0x7f;
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if (ctop) {
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// my_printf ("call %%ctpr%d, wbs = 0x%x", ctop, wbs);
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// print_ctcond (info, instr->ss & 0x1ff);
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} else {
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unsigned int cs1_ctopc = (cs1 & 0x380) >> 7;
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/* CS1.param.ctpopc == HCALL. CS0 is required to encode HCALL. */
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if (cs1_ctopc == 2 && bundle->cs0_present) {
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unsigned int cs0 = bundle->cs0;
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unsigned int cs0_opc = (cs0 & 0xf0000000) >> 28;
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/* CS0.opc == HCALL, which means
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CS0.opc.ctpr == CS0.opc.ctp_opc == 0 */
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if (cs0_opc == 0) {
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// unsigned int hdisp = (cs0 & 0x1e) >> 1;
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// my_printf ("hcall 0x%x, wbs = 0x%x", hdisp, wbs);
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// print_ctcond (info, instr->ss & 0x1ff);
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}
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} else {
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// my_printf ("<bogus call>");
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}
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}
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} else if (opc == MAS_OPC) {
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/* Note that LDIS doesn't print it out as a standalone instruction. */
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// unsigned int mas = cs1 & 0x0fffffff;
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// my_printf ("mas 0x%x", mas);
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} else if (opc == FLUSHR) {
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/* . . . these stupid engineers off! FLUSHR seems to be responsible for
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encoding both `flushr' and `flushc'. Moreover, according to their
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logic it should be possible to encode them simultaneously. */
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/* Check for `CS1.param.flr'. */
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if (cs1 & 0x00000001) {
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// my_printf ("flushr");
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}
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/* Check for `CS1.param.flc'. */
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if (cs1 & 0x00000002) {
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// my_printf ("flushc");
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}
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} else if (opc == BG) {
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/* Hopefully, `vfbg' is the only instruction encoded by BG. I'm currently
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unable to find other ones in `iset-v5.single' at least . . . */
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// unsigned int chkm4 = (cs1 & 0x00010000) >> 16;
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// unsigned int dmask = (cs1 & 0x0000ff00) >> 8;
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// unsigned int umsk = cs1 & 0x000000ff;
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/* Print its fields in the order proposed in C.14.10. */
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// my_printf ("vfbg umask = 0x%x, dmask = 0x%x, chkm4 = 0x%x",
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// umsk, dmask, chkm4);
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} else {
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// my_printf ("unimp");
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abort();
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}
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}
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static void gen_jmp(DisasContext *dc)
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{
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unsigned int ctcond = GET_FIELD(dc->bundle.ss, 0, 8);
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unsigned int cond_type = (ctcond & 0x1e0) >> 5;
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unsigned int psrc = (ctcond & 0x01f);
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/* TODO: check CPU behavior if present ibranch and ctpr is not zero */
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if (cond_type == 1) {
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dc->base.is_jmp = STATIC_JUMP;
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tcg_gen_movi_i64(dc->jmp.cond, 1);
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return;
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}
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dc->base.is_jmp = DYNAMIC_JUMP;
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if (cond_type == 2 || cond_type == 6 || cond_type == 0xf) {
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/* if pred is true */
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tcg_gen_mov_i64(dc->jmp.cond, e2k_get_preg(dc, psrc));
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} else if (cond_type == 3 || cond_type == 7 || cond_type == 0xe) {
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/* if pred is false */
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TCGv_i64 one = tcg_const_i64(1);
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TCGv_i64 zero = tcg_const_i64(0);
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tcg_gen_movcond_i64(TCG_COND_EQ, dc->jmp.cond,
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e2k_get_preg(dc, psrc), zero,
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one, zero);
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tcg_temp_free_i64(zero);
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tcg_temp_free_i64(one);
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}
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/* TODO: other kinds of conditions */
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if (cond_type == 4
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|| cond_type == 6
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|| cond_type == 0xe)
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{
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if (cond_type == 6 || cond_type == 0xe) {
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// or
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}
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// %LOOP_END
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}
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if (cond_type == 5
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|| cond_type == 7
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|| cond_type == 0xf)
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{
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if(cond_type == 7
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|| cond_type == 0xf)
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{
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// AND
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}
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// %NOT_LOOP_END
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}
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if (cond_type == 8) {
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// %MLOCK
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/* It's not clearly said in C.17.1.2 of iset-vX.single if the uppermost
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fourth bit in `psrc' has any meaning at all. */
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if (psrc & 0xf) {
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// static const int conv[] = {0, 1, 3, 4};
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int i;
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// %dt_al
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for (i = 0; i < 4; i++) {
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if (psrc & (1 << i)) {
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// i
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}
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}
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}
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}
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/* `lock_cond || pl_cond' control transfer conditions. */
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if (cond_type == 9) {
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unsigned int type = (psrc & 0x18) >> 3;
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if (type == 0) {
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// static const int cmp_num_to_alc[] = {0, 1, 3, 4};
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// unsigned int cmp_num = (psrc & 0x6) >> 1;
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// unsigned int neg = psrc & 0x1;
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// my_printf ("%%MLOCK || %s%%cmp%d", neg ? "~" : "",
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// cmp_num_to_alc[cmp_num]);
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} else if (type == 1) {
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// unsigned int cmp_jk = (psrc & 0x4) >> 2;
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// unsigned int negj = (psrc & 0x2) >> 1;
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// unsigned int negk = psrc & 0x1;
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// my_printf ("%%MLOCK || %s%%cmp%d || %s%%cmp%d",
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// negj ? "~" : "", cmp_jk == 0 ? 0 : 3,
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// negk ? "~" : "", cmp_jk == 0 ? 1 : 4);
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} else if (type == 2) {
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// unsigned int clp_num = (psrc & 0x6) >> 1;
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// unsigned int neg = psrc & 0x1;
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// "%%MLOCK || %s%%clp%d", neg ? "~" : "", clp_num
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}
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}
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if (cond_type >= 0xa && cond_type <= 0xd) {
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// reserved condition type
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qemu_log_mask(LOG_UNIMP, "Undefined control transfer type %#x\n", cond_type);
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abort();
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}
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}
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void e2k_control_gen(DisasContext *dc)
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{
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if (dc->bundle.cs0_present) {
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gen_cs0(dc);
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}
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if (dc->bundle.cs1_present) {
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gen_cs1(dc);
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}
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if (dc->bundle.ss_present) {
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gen_jmp(dc);
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}
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}
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