qemu-e2k/target/riscv/insn_trans
Kiran Ostrolenk a44f19f611 target/riscv: Refactor vector-vector translation macro
Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.

Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20230711165917.2629866-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-09-11 11:45:54 +10:00
..
trans_privileged.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_rva.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvb.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvbf16.c.inc target/riscv: Add support for Zvfbfwma extension 2023-07-10 22:29:15 +10:00
trans_rvd.c.inc target/riscv: Update check for Zca/Zcf/Zcd 2023-06-13 17:01:30 +10:00
trans_rvf.c.inc riscv: spelling fixes 2023-09-08 13:08:52 +03:00
trans_rvh.c.inc target/riscv: Handle HLV, HSV via helpers 2023-05-05 10:49:50 +10:00
trans_rvi.c.inc target/riscv: Enable PC-relative translation 2023-06-13 17:37:12 +10:00
trans_rvk.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvm.c.inc target/riscv: Drop tcg_temp_free 2023-03-05 13:44:08 -08:00
trans_rvv.c.inc target/riscv: Refactor vector-vector translation macro 2023-09-11 11:45:54 +10:00
trans_rvzawrs.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_rvzce.c.inc target/riscv: Enable PC-relative translation 2023-06-13 17:37:12 +10:00
trans_rvzfa.c.inc riscv: Add support for the Zfa extension 2023-07-10 22:29:20 +10:00
trans_rvzfh.c.inc riscv: spelling fixes 2023-09-08 13:08:52 +03:00
trans_rvzicbo.c.inc target/riscv: implement Zicbom extension 2023-03-05 11:49:42 -08:00
trans_rvzicond.c.inc target/riscv: refactor Zicond support 2023-05-05 10:49:50 +10:00
trans_svinval.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_xthead.c.inc target/riscv: Change gen_set_pc_imm to gen_update_pc 2023-06-13 17:35:20 +10:00
trans_xventanacondops.c.inc target/riscv: redirect XVentanaCondOps to use the Zicond functions 2023-05-05 10:49:50 +10:00