e4ea952fb0
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-41-richard.henderson@linaro.org>
210 lines
6.9 KiB
C
210 lines
6.9 KiB
C
/*
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* Allwinner R40 Clock Control Unit emulation
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*
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* Copyright (C) 2023 qianfan Zhao <qianfanguijin@163.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/misc/allwinner-r40-ccu.h"
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/* CCU register offsets */
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enum {
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REG_PLL_CPUX_CTRL = 0x0000,
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REG_PLL_AUDIO_CTRL = 0x0008,
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REG_PLL_VIDEO0_CTRL = 0x0010,
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REG_PLL_VE_CTRL = 0x0018,
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REG_PLL_DDR0_CTRL = 0x0020,
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REG_PLL_PERIPH0_CTRL = 0x0028,
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REG_PLL_PERIPH1_CTRL = 0x002c,
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REG_PLL_VIDEO1_CTRL = 0x0030,
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REG_PLL_SATA_CTRL = 0x0034,
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REG_PLL_GPU_CTRL = 0x0038,
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REG_PLL_MIPI_CTRL = 0x0040,
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REG_PLL_DE_CTRL = 0x0048,
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REG_PLL_DDR1_CTRL = 0x004c,
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REG_AHB1_APB1_CFG = 0x0054,
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REG_APB2_CFG = 0x0058,
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REG_MMC0_CLK = 0x0088,
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REG_MMC1_CLK = 0x008c,
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REG_MMC2_CLK = 0x0090,
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REG_MMC3_CLK = 0x0094,
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REG_USBPHY_CFG = 0x00cc,
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REG_PLL_DDR_AUX = 0x00f0,
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REG_DRAM_CFG = 0x00f4,
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REG_PLL_DDR1_CFG = 0x00f8,
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REG_DRAM_CLK_GATING = 0x0100,
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REG_GMAC_CLK = 0x0164,
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REG_SYS_32K_CLK = 0x0310,
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REG_PLL_LOCK_CTRL = 0x0320,
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};
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#define REG_INDEX(offset) (offset / sizeof(uint32_t))
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/* CCU register flags */
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enum {
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REG_PLL_ENABLE = (1 << 31),
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REG_PLL_LOCK = (1 << 28),
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};
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static uint64_t allwinner_r40_ccu_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwR40ClockCtlState *s = AW_R40_CCU(opaque);
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const uint32_t idx = REG_INDEX(offset);
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switch (offset) {
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case 0x324 ... AW_R40_CCU_IOSIZE:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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return s->regs[idx];
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}
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static void allwinner_r40_ccu_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwR40ClockCtlState *s = AW_R40_CCU(opaque);
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switch (offset) {
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case REG_DRAM_CFG: /* DRAM Configuration(for DDR0) */
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/* bit16: SDRCLK_UPD (SDRCLK configuration 0 update) */
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val &= ~(1 << 16);
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break;
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case REG_PLL_DDR1_CTRL: /* DDR1 Control register */
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/* bit30: SDRPLL_UPD */
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val &= ~(1 << 30);
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if (val & REG_PLL_ENABLE) {
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val |= REG_PLL_LOCK;
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}
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break;
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case REG_PLL_CPUX_CTRL:
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case REG_PLL_AUDIO_CTRL:
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case REG_PLL_VE_CTRL:
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case REG_PLL_VIDEO0_CTRL:
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case REG_PLL_DDR0_CTRL:
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case REG_PLL_PERIPH0_CTRL:
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case REG_PLL_PERIPH1_CTRL:
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case REG_PLL_VIDEO1_CTRL:
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case REG_PLL_SATA_CTRL:
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case REG_PLL_GPU_CTRL:
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case REG_PLL_MIPI_CTRL:
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case REG_PLL_DE_CTRL:
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if (val & REG_PLL_ENABLE) {
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val |= REG_PLL_LOCK;
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}
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break;
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case 0x324 ... AW_R40_CCU_IOSIZE:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
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__func__, (uint32_t)offset);
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break;
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}
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s->regs[REG_INDEX(offset)] = (uint32_t) val;
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}
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static const MemoryRegionOps allwinner_r40_ccu_ops = {
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.read = allwinner_r40_ccu_read,
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.write = allwinner_r40_ccu_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static void allwinner_r40_ccu_reset(DeviceState *dev)
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{
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AwR40ClockCtlState *s = AW_R40_CCU(dev);
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memset(s->regs, 0, sizeof(s->regs));
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/* Set default values for registers */
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s->regs[REG_INDEX(REG_PLL_CPUX_CTRL)] = 0x00001000;
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s->regs[REG_INDEX(REG_PLL_AUDIO_CTRL)] = 0x00035514;
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s->regs[REG_INDEX(REG_PLL_VIDEO0_CTRL)] = 0x03006207;
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s->regs[REG_INDEX(REG_PLL_VE_CTRL)] = 0x03006207;
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s->regs[REG_INDEX(REG_PLL_DDR0_CTRL)] = 0x00001000,
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s->regs[REG_INDEX(REG_PLL_PERIPH0_CTRL)] = 0x00041811;
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s->regs[REG_INDEX(REG_PLL_PERIPH1_CTRL)] = 0x00041811;
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s->regs[REG_INDEX(REG_PLL_VIDEO1_CTRL)] = 0x03006207;
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s->regs[REG_INDEX(REG_PLL_SATA_CTRL)] = 0x00001811;
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s->regs[REG_INDEX(REG_PLL_GPU_CTRL)] = 0x03006207;
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s->regs[REG_INDEX(REG_PLL_MIPI_CTRL)] = 0x00000515;
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s->regs[REG_INDEX(REG_PLL_DE_CTRL)] = 0x03006207;
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s->regs[REG_INDEX(REG_PLL_DDR1_CTRL)] = 0x00001800;
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s->regs[REG_INDEX(REG_AHB1_APB1_CFG)] = 0x00001010;
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s->regs[REG_INDEX(REG_APB2_CFG)] = 0x01000000;
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s->regs[REG_INDEX(REG_PLL_DDR_AUX)] = 0x00000001;
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s->regs[REG_INDEX(REG_PLL_DDR1_CFG)] = 0x0ccca000;
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s->regs[REG_INDEX(REG_SYS_32K_CLK)] = 0x0000000f;
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}
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static void allwinner_r40_ccu_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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AwR40ClockCtlState *s = AW_R40_CCU(obj);
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/* Memory mapping */
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memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_r40_ccu_ops, s,
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TYPE_AW_R40_CCU, AW_R40_CCU_IOSIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription allwinner_r40_ccu_vmstate = {
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.name = "allwinner-r40-ccu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AwR40ClockCtlState, AW_R40_CCU_REGS_NUM),
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VMSTATE_END_OF_LIST()
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}
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};
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static void allwinner_r40_ccu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = allwinner_r40_ccu_reset;
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dc->vmsd = &allwinner_r40_ccu_vmstate;
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}
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static const TypeInfo allwinner_r40_ccu_info = {
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.name = TYPE_AW_R40_CCU,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = allwinner_r40_ccu_init,
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.instance_size = sizeof(AwR40ClockCtlState),
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.class_init = allwinner_r40_ccu_class_init,
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};
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static void allwinner_r40_ccu_register(void)
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{
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type_register_static(&allwinner_r40_ccu_info);
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}
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type_init(allwinner_r40_ccu_register)
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