54f59d786c
The Processor Service Interface (PSI) Controller is one of the engines of the "Bridge" unit which connects the different interfaces to the Power Processor. This adds just enough of the PSI bridge to handle various on-chip and the one external interrupt. The rest of PSI has to do with the link to the IBM FSP service processor which we don't plan to emulate (not used on OpenPower machines). The ics_get() and ics_resend() handlers of the XICSFabric interface of the PowerNV machine are now defined to handle the Interrupt Control Source of PSI. The InterruptStatsProvider interface is also modified to dump the new ICS. Originally from Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/*
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* QEMU PowerPC PowerNV Processor Service Interface (PSI) model
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*
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* Copyright (c) 2015-2017, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _PPC_PNV_PSI_H
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#define _PPC_PNV_PSI_H
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#include "hw/sysbus.h"
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#include "hw/ppc/xics.h"
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#define TYPE_PNV_PSI "pnv-psi"
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#define PNV_PSI(obj) \
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OBJECT_CHECK(PnvPsi, (obj), TYPE_PNV_PSI)
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#define PSIHB_XSCOM_MAX 0x20
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typedef struct XICSState XICSState;
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typedef struct PnvPsi {
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SysBusDevice parent;
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MemoryRegion regs_mr;
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uint64_t bar;
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/* FSP region not supported */
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/* MemoryRegion fsp_mr; */
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uint64_t fsp_bar;
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/* Interrupt generation */
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ICSState ics;
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/* Registers */
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uint64_t regs[PSIHB_XSCOM_MAX];
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MemoryRegion xscom_regs;
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} PnvPsi;
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/* The PSI and FSP interrupts are muxed on the same IRQ number */
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typedef enum PnvPsiIrq {
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PSIHB_IRQ_PSI, /* internal use only */
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PSIHB_IRQ_FSP, /* internal use only */
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PSIHB_IRQ_OCC,
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PSIHB_IRQ_FSI,
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PSIHB_IRQ_LPC_I2C,
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PSIHB_IRQ_LOCAL_ERR,
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PSIHB_IRQ_EXTERNAL,
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} PnvPsiIrq;
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#define PSI_NUM_INTERRUPTS 6
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extern void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state);
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#endif /* _PPC_PNV_PSI_H */
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