Peter Maydell a59b1ed618 target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry ... In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR are zeroed for an exception taken to Non-secure state; for an exception taken to Secure state they become UNKNOWN, and we chose to leave them at their previous values. In v8.1M the behaviour is specified more tightly and these registers are always zeroed regardless of the security state that the exception targets (see rule R_KPZV). Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-17-peter.maydell@linaro.org		2020-12-10 11:44:55 +00:00
..
a32-uncond.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
a32.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
arch_dump.c	target/arm: add spaces around operator	2020-11-10 11:03:47 +00:00
arm_ldst.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
arm-powerctl.c
arm-powerctl.h
arm-semi.c	target/arm: Make SYS_HEAPINFO work with RAM that doesn't start at 0	2020-11-23 11:03:27 +00:00
cpu64.c	target/arm: Make '-cpu max' have a 48-bit PA	2020-10-08 21:40:01 +01:00
cpu_tcg.c	target/arm: Add ID register values for Cortex-M0	2020-10-01 15:31:00 +01:00
cpu-param.h
cpu-qom.h	qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros	2020-09-18 14:12:32 -04:00
cpu.c	hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M	2020-12-10 11:44:55 +00:00
cpu.h	hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M	2020-12-10 11:44:55 +00:00
crypto_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
debug_helper.c
gdbstub64.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
gdbstub.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
helper-a64.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
helper-a64.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
helper-sve.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
helper.c	target/arm: Implement v8.1M PXN extension	2020-12-10 11:44:55 +00:00
helper.h	target/arm: Fix neon VTBL/VTBX for len > 1	2020-11-10 11:03:48 +00:00
idau.h	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00
internals.h	target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11	2020-10-20 16:12:00 +01:00
iwmmxt_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
kvm64.c	hw/arm/virt: Implement kvm-steal-time	2020-10-08 15:24:32 +01:00
kvm_arm.h	hw/arm/virt: Implement kvm-steal-time	2020-10-08 15:24:32 +01:00
kvm-consts.h	target/arm: Remove no-longer-reachable 32-bit KVM code	2020-09-14 14:23:19 +01:00
kvm-stub.c
kvm.c	hw/arm/virt: Implement kvm-steal-time	2020-10-08 15:24:32 +01:00
m_helper.c	target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry	2020-12-10 11:44:55 +00:00
m-nocp.decode	target/arm: Implement VSCCLRM insn	2020-12-10 11:44:55 +00:00
machine.c
meson.build	target/arm: Remove KVM support for 32-bit Arm hosts	2020-09-14 14:23:19 +01:00
monitor.c	hw/arm/virt: Implement kvm-steal-time	2020-10-08 15:24:32 +01:00
mte_helper.c	target/arm: Fix reported EL for mte_check_fail	2020-10-20 16:12:00 +01:00
neon_helper.c
neon-dp.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
neon-ls.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
neon-shared.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
op_addsub.h
op_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
pauth_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
psci.c
sve_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
sve.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
t16.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
t32.decode	target/arm: Implement CLRM instruction	2020-12-10 11:44:55 +00:00
tlb_helper.c
trace-events
trace.h
translate-a64.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
translate-a64.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
translate-neon.c.inc	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
translate-sve.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
translate-vfp.c.inc	target/arm: Implement FPCXT_S fp system register	2020-12-10 11:44:55 +00:00
translate.c	target/arm: Move general-use constant expanders up in translate.c	2020-12-10 11:44:55 +00:00
translate.h
vec_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
vec_internal.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
vfp_helper.c	target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension	2020-10-20 16:12:01 +01:00
vfp-uncond.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
vfp.decode	target/arm: Implement VLDR/VSTR system register	2020-12-10 11:44:55 +00:00