487 lines
14 KiB
C
487 lines
14 KiB
C
/*
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Author: Prem Mallappa <pmallapp@broadcom.com>
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*
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*/
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#include "qemu/osdep.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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#include "exec/target_page.h"
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#include "qom/cpu.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qemu/jhash.h"
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#include "qemu/error-report.h"
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#include "hw/arm/smmu-common.h"
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#include "smmu-internal.h"
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/* IOTLB Management */
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inline void smmu_iotlb_inv_all(SMMUState *s)
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{
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trace_smmu_iotlb_inv_all();
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g_hash_table_remove_all(s->iotlb);
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}
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static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
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gpointer user_data)
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{
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uint16_t asid = *(uint16_t *)user_data;
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SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key;
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return iotlb_key->asid == asid;
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}
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inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova)
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{
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SMMUIOTLBKey key = {.asid = asid, .iova = iova};
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trace_smmu_iotlb_inv_iova(asid, iova);
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g_hash_table_remove(s->iotlb, &key);
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}
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inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
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{
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trace_smmu_iotlb_inv_asid(asid);
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g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
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}
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/* VMSAv8-64 Translation */
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/**
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* get_pte - Get the content of a page table entry located at
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* @base_addr[@index]
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*/
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static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,
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SMMUPTWEventInfo *info)
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{
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int ret;
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dma_addr_t addr = baseaddr + index * sizeof(*pte);
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/* TODO: guarantee 64-bit single-copy atomicity */
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ret = dma_memory_read(&address_space_memory, addr,
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(uint8_t *)pte, sizeof(*pte));
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if (ret != MEMTX_OK) {
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info->type = SMMU_PTW_ERR_WALK_EABT;
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info->addr = addr;
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return -EINVAL;
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}
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trace_smmu_get_pte(baseaddr, index, addr, *pte);
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return 0;
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}
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/* VMSAv8-64 Translation Table Format Descriptor Decoding */
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/**
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* get_page_pte_address - returns the L3 descriptor output address,
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* ie. the page frame
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* ARM ARM spec: Figure D4-17 VMSAv8-64 level 3 descriptor format
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*/
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static inline hwaddr get_page_pte_address(uint64_t pte, int granule_sz)
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{
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return PTE_ADDRESS(pte, granule_sz);
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}
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/**
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* get_table_pte_address - return table descriptor output address,
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* ie. address of next level table
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* ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
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*/
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static inline hwaddr get_table_pte_address(uint64_t pte, int granule_sz)
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{
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return PTE_ADDRESS(pte, granule_sz);
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}
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/**
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* get_block_pte_address - return block descriptor output address and block size
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* ARM ARM Figure D4-16 VMSAv8-64 level0, level1, and level 2 descriptor formats
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*/
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static inline hwaddr get_block_pte_address(uint64_t pte, int level,
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int granule_sz, uint64_t *bsz)
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{
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int n = level_shift(level, granule_sz);
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*bsz = 1ULL << n;
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return PTE_ADDRESS(pte, n);
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}
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SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
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{
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bool tbi = extract64(iova, 55, 1) ? TBI1(cfg->tbi) : TBI0(cfg->tbi);
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uint8_t tbi_byte = tbi * 8;
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if (cfg->tt[0].tsz &&
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!extract64(iova, 64 - cfg->tt[0].tsz, cfg->tt[0].tsz - tbi_byte)) {
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/* there is a ttbr0 region and we are in it (high bits all zero) */
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return &cfg->tt[0];
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} else if (cfg->tt[1].tsz &&
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!extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
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/* there is a ttbr1 region and we are in it (high bits all one) */
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return &cfg->tt[1];
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} else if (!cfg->tt[0].tsz) {
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/* ttbr0 region is "everything not in the ttbr1 region" */
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return &cfg->tt[0];
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} else if (!cfg->tt[1].tsz) {
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/* ttbr1 region is "everything not in the ttbr0 region" */
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return &cfg->tt[1];
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}
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/* in the gap between the two regions, this is a Translation fault */
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return NULL;
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}
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/**
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* smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA
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* @cfg: translation config
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* @iova: iova to translate
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* @perm: access type
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* @tlbe: IOMMUTLBEntry (out)
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* @info: handle to an error info
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*
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* Return 0 on success, < 0 on error. In case of error, @info is filled
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* and tlbe->perm is set to IOMMU_NONE.
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* Upon success, @tlbe is filled with translated_addr and entry
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* permission rights.
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*/
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static int smmu_ptw_64(SMMUTransCfg *cfg,
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dma_addr_t iova, IOMMUAccessFlags perm,
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IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
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{
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dma_addr_t baseaddr, indexmask;
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int stage = cfg->stage;
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SMMUTransTableInfo *tt = select_tt(cfg, iova);
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uint8_t level, granule_sz, inputsize, stride;
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if (!tt || tt->disabled) {
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info->type = SMMU_PTW_ERR_TRANSLATION;
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goto error;
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}
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granule_sz = tt->granule_sz;
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stride = granule_sz - 3;
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inputsize = 64 - tt->tsz;
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level = 4 - (inputsize - 4) / stride;
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indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
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baseaddr = extract64(tt->ttb, 0, 48);
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baseaddr &= ~indexmask;
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tlbe->iova = iova;
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tlbe->addr_mask = (1 << granule_sz) - 1;
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while (level <= 3) {
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uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
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uint64_t mask = subpage_size - 1;
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uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz);
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uint64_t pte;
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dma_addr_t pte_addr = baseaddr + offset * sizeof(pte);
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uint8_t ap;
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if (get_pte(baseaddr, offset, &pte, info)) {
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goto error;
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}
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trace_smmu_ptw_level(level, iova, subpage_size,
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baseaddr, offset, pte);
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if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
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trace_smmu_ptw_invalid_pte(stage, level, baseaddr,
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pte_addr, offset, pte);
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info->type = SMMU_PTW_ERR_TRANSLATION;
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goto error;
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}
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if (is_page_pte(pte, level)) {
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uint64_t gpa = get_page_pte_address(pte, granule_sz);
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ap = PTE_AP(pte);
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if (is_permission_fault(ap, perm)) {
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info->type = SMMU_PTW_ERR_PERMISSION;
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goto error;
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}
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tlbe->translated_addr = gpa + (iova & mask);
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tlbe->perm = PTE_AP_TO_PERM(ap);
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trace_smmu_ptw_page_pte(stage, level, iova,
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baseaddr, pte_addr, pte, gpa);
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return 0;
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}
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if (is_block_pte(pte, level)) {
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uint64_t block_size;
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hwaddr gpa = get_block_pte_address(pte, level, granule_sz,
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&block_size);
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ap = PTE_AP(pte);
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if (is_permission_fault(ap, perm)) {
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info->type = SMMU_PTW_ERR_PERMISSION;
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goto error;
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}
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trace_smmu_ptw_block_pte(stage, level, baseaddr,
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pte_addr, pte, iova, gpa,
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block_size >> 20);
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tlbe->translated_addr = gpa + (iova & mask);
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tlbe->perm = PTE_AP_TO_PERM(ap);
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return 0;
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}
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/* table pte */
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ap = PTE_APTABLE(pte);
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if (is_permission_fault(ap, perm)) {
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info->type = SMMU_PTW_ERR_PERMISSION;
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goto error;
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}
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baseaddr = get_table_pte_address(pte, granule_sz);
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level++;
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}
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info->type = SMMU_PTW_ERR_TRANSLATION;
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error:
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tlbe->perm = IOMMU_NONE;
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return -EINVAL;
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}
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/**
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* smmu_ptw - Walk the page tables for an IOVA, according to @cfg
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*
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* @cfg: translation configuration
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* @iova: iova to translate
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* @perm: tentative access type
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* @tlbe: returned entry
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* @info: ptw event handle
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*
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* return 0 on success
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*/
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inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
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IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
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{
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if (!cfg->aa64) {
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/*
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* This code path is not entered as we check this while decoding
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* the configuration data in the derived SMMU model.
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*/
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g_assert_not_reached();
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}
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return smmu_ptw_64(cfg, iova, perm, tlbe, info);
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}
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/**
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* The bus number is used for lookup when SID based invalidation occurs.
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* In that case we lazily populate the SMMUPciBus array from the bus hash
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* table. At the time the SMMUPciBus is created (smmu_find_add_as), the bus
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* numbers may not be always initialized yet.
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*/
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SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num)
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{
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SMMUPciBus *smmu_pci_bus = s->smmu_pcibus_by_bus_num[bus_num];
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if (!smmu_pci_bus) {
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GHashTableIter iter;
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g_hash_table_iter_init(&iter, s->smmu_pcibus_by_busptr);
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while (g_hash_table_iter_next(&iter, NULL, (void **)&smmu_pci_bus)) {
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if (pci_bus_num(smmu_pci_bus->bus) == bus_num) {
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s->smmu_pcibus_by_bus_num[bus_num] = smmu_pci_bus;
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return smmu_pci_bus;
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}
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}
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}
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return smmu_pci_bus;
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}
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static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
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{
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SMMUState *s = opaque;
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SMMUPciBus *sbus = g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus);
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SMMUDevice *sdev;
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static unsigned int index;
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if (!sbus) {
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sbus = g_malloc0(sizeof(SMMUPciBus) +
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sizeof(SMMUDevice *) * SMMU_PCI_DEVFN_MAX);
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sbus->bus = bus;
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g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus);
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}
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sdev = sbus->pbdev[devfn];
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if (!sdev) {
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char *name = g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, index++);
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sdev = sbus->pbdev[devfn] = g_new0(SMMUDevice, 1);
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sdev->smmu = s;
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sdev->bus = bus;
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sdev->devfn = devfn;
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memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
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s->mrtypename,
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OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
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address_space_init(&sdev->as,
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MEMORY_REGION(&sdev->iommu), name);
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trace_smmu_add_mr(name);
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g_free(name);
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}
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return &sdev->as;
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}
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IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
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{
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uint8_t bus_n, devfn;
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SMMUPciBus *smmu_bus;
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SMMUDevice *smmu;
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bus_n = PCI_BUS_NUM(sid);
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smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
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if (smmu_bus) {
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devfn = SMMU_PCI_DEVFN(sid);
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smmu = smmu_bus->pbdev[devfn];
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if (smmu) {
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return &smmu->iommu;
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}
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}
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return NULL;
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}
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static guint smmu_iotlb_key_hash(gconstpointer v)
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{
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SMMUIOTLBKey *key = (SMMUIOTLBKey *)v;
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uint32_t a, b, c;
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/* Jenkins hash */
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a = b = c = JHASH_INITVAL + sizeof(*key);
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a += key->asid;
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b += extract64(key->iova, 0, 32);
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c += extract64(key->iova, 32, 32);
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__jhash_mix(a, b, c);
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__jhash_final(a, b, c);
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return c;
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}
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static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2)
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{
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const SMMUIOTLBKey *k1 = v1;
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const SMMUIOTLBKey *k2 = v2;
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return (k1->asid == k2->asid) && (k1->iova == k2->iova);
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}
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/* Unmap the whole notifier's range */
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static void smmu_unmap_notifier_range(IOMMUNotifier *n)
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{
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IOMMUTLBEntry entry;
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entry.target_as = &address_space_memory;
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entry.iova = n->start;
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entry.perm = IOMMU_NONE;
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entry.addr_mask = n->end - n->start;
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memory_region_notify_one(n, &entry);
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}
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/* Unmap all notifiers attached to @mr */
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inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
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{
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IOMMUNotifier *n;
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trace_smmu_inv_notifiers_mr(mr->parent_obj.name);
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IOMMU_NOTIFIER_FOREACH(n, mr) {
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smmu_unmap_notifier_range(n);
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}
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}
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/* Unmap all notifiers of all mr's */
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void smmu_inv_notifiers_all(SMMUState *s)
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{
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SMMUNotifierNode *node;
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QLIST_FOREACH(node, &s->notifiers_list, next) {
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smmu_inv_notifiers_mr(&node->sdev->iommu);
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}
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}
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static void smmu_base_realize(DeviceState *dev, Error **errp)
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{
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SMMUState *s = ARM_SMMU(dev);
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SMMUBaseClass *sbc = ARM_SMMU_GET_CLASS(dev);
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Error *local_err = NULL;
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sbc->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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s->configs = g_hash_table_new_full(NULL, NULL, NULL, g_free);
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s->iotlb = g_hash_table_new_full(smmu_iotlb_key_hash, smmu_iotlb_key_equal,
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g_free, g_free);
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s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL);
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if (s->primary_bus) {
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pci_setup_iommu(s->primary_bus, smmu_find_add_as, s);
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} else {
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error_setg(errp, "SMMU is not attached to any PCI bus!");
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}
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}
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static void smmu_base_reset(DeviceState *dev)
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{
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SMMUState *s = ARM_SMMU(dev);
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g_hash_table_remove_all(s->configs);
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g_hash_table_remove_all(s->iotlb);
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}
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static Property smmu_dev_properties[] = {
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DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0),
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DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, "PCI", PCIBus *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void smmu_base_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
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dc->props = smmu_dev_properties;
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device_class_set_parent_realize(dc, smmu_base_realize,
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&sbc->parent_realize);
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dc->reset = smmu_base_reset;
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}
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static const TypeInfo smmu_base_info = {
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.name = TYPE_ARM_SMMU,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SMMUState),
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.class_data = NULL,
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.class_size = sizeof(SMMUBaseClass),
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.class_init = smmu_base_class_init,
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.abstract = true,
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};
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static void smmu_base_register_types(void)
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{
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type_register_static(&smmu_base_info);
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}
|
|
|
|
type_init(smmu_base_register_types)
|
|
|