1a9b30646e
If the CMSDK APB timer is set up with a zero RELOAD value then it will count down to zero, fire once and then stay at zero. From the point of view of the ptimer system, the timer is disabled; but the enable bit in the CTRL register is still set and if the guest subsequently writes to the RELOAD or VALUE registers this should cause the timer to start counting down again. Add code to the write paths for RELOAD and VALUE so that we correctly restart the timer in this situation. Conversely, if the new RELOAD and VALUE are both zero, we should stop the ptimer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20180703171044.9503-5-peter.maydell@linaro.org |
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| .. | ||
| Makefile.objs | ||
| a9gtimer.c | ||
| allwinner-a10-pit.c | ||
| altera_timer.c | ||
| arm_mptimer.c | ||
| arm_timer.c | ||
| armv7m_systick.c | ||
| aspeed_timer.c | ||
| cadence_ttc.c | ||
| cmsdk-apb-timer.c | ||
| digic-timer.c | ||
| ds1338.c | ||
| etraxfs_timer.c | ||
| exynos4210_mct.c | ||
| exynos4210_pwm.c | ||
| exynos4210_rtc.c | ||
| grlib_gptimer.c | ||
| hpet.c | ||
| i8254.c | ||
| i8254_common.c | ||
| imx_epit.c | ||
| imx_gpt.c | ||
| lm32_timer.c | ||
| m41t80.c | ||
| m48t59-internal.h | ||
| m48t59-isa.c | ||
| m48t59.c | ||
| mc146818rtc.c | ||
| milkymist-sysctl.c | ||
| mips_gictimer.c | ||
| mss-timer.c | ||
| omap_gptimer.c | ||
| omap_synctimer.c | ||
| pl031.c | ||
| puv3_ost.c | ||
| pxa2xx_timer.c | ||
| sh_timer.c | ||
| slavio_timer.c | ||
| stm32f2xx_timer.c | ||
| sun4v-rtc.c | ||
| trace-events | ||
| twl92230.c | ||
| xilinx_timer.c | ||
| xlnx-zynqmp-rtc.c | ||