a7172791e3
We extend RISC-V spike machine to allow creating a multi-socket machine. Each RISC-V spike machine socket is a NUMA node having a set of HARTs, a memory instance, and a CLINT instance. Other devices are shared between all sockets. We also update the generated device tree accordingly. By default, NUMA multi-socket support is disabled for RISC-V spike machine. To enable it, users can use "-numa" command-line options of QEMU. Example1: For two NUMA nodes with 2 CPUs each, append following to command-line options: "-smp 4 -numa node -numa node" Example2: For two NUMA nodes with 1 and 3 CPUs, append following to command-line options: "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \ -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \ -numa cpu,node-id=1,core-id=3" The maximum number of sockets in a RISC-V spike machine is 8 but this limit can be changed in future. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Message-Id: <20200616032229.766089-5-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/*
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* Spike machine interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_SPIKE_H
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#define HW_RISCV_SPIKE_H
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#include "hw/riscv/riscv_hart.h"
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#include "hw/sysbus.h"
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#define SPIKE_CPUS_MAX 8
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#define SPIKE_SOCKETS_MAX 8
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#define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike")
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#define SPIKE_MACHINE(obj) \
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OBJECT_CHECK(SpikeState, (obj), TYPE_SPIKE_MACHINE)
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typedef struct {
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/*< private >*/
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MachineState parent;
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/*< public >*/
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RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
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void *fdt;
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int fdt_size;
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} SpikeState;
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enum {
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SPIKE_MROM,
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SPIKE_CLINT,
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SPIKE_DRAM
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};
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#if defined(TARGET_RISCV32)
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
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#elif defined(TARGET_RISCV64)
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#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
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#endif
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#endif
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