ea9cea93c6
Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-5-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
311 lines
15 KiB
C
311 lines
15 KiB
C
/*
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* xtensa/config/core-matmap.h -- Memory access and translation mapping
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* parameters (CHAL) of the Xtensa processor core configuration.
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*
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* If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
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* this file) for more details.
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*
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* In the Xtensa processor products released to date, all parameters
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* defined in this file are derivable (at least in theory) from
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* information contained in the core-isa.h header file.
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* In particular, the following core configuration parameters are relevant:
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* XCHAL_HAVE_CACHEATTR
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* XCHAL_HAVE_MIMIC_CACHEATTR
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* XCHAL_HAVE_XLT_CACHEATTR
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* XCHAL_HAVE_PTP_MMU
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* XCHAL_ITLB_ARF_ENTRIES_LOG2
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* XCHAL_DTLB_ARF_ENTRIES_LOG2
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* XCHAL_DCACHE_IS_WRITEBACK
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* XCHAL_ICACHE_SIZE (presence of I-cache)
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* XCHAL_DCACHE_SIZE (presence of D-cache)
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* XCHAL_HW_VERSION_MAJOR
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* XCHAL_HW_VERSION_MINOR
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*/
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/* Copyright (c) 1999-2010 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef XTENSA_CONFIG_CORE_MATMAP_H
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#define XTENSA_CONFIG_CORE_MATMAP_H
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/*----------------------------------------------------------------------
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CACHE (MEMORY ACCESS) ATTRIBUTES
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----------------------------------------------------------------------*/
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/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
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#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_CACHED XCHAL_SEP \
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XTHAL_FAM_BYPASS XCHAL_SEP \
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XTHAL_FAM_CACHED XCHAL_SEP \
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XTHAL_FAM_CACHED XCHAL_SEP \
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XTHAL_FAM_CACHED XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION XCHAL_SEP \
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XTHAL_FAM_EXCEPTION
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#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \
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XTHAL_LAM_CACHED XCHAL_SEP \
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XTHAL_LAM_BYPASSG XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_CACHED XCHAL_SEP \
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XTHAL_LAM_CACHED XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_EXCEPTION XCHAL_SEP \
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XTHAL_LAM_ISOLATE XCHAL_SEP \
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XTHAL_LAM_EXCEPTION
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#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
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XTHAL_SAM_WRITETHRU XCHAL_SEP \
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XTHAL_SAM_BYPASS XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_WRITEBACK XCHAL_SEP \
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XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_EXCEPTION XCHAL_SEP \
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XTHAL_SAM_ISOLATE XCHAL_SEP \
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XTHAL_SAM_EXCEPTION
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/*
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* Specific encoded cache attribute values of general interest.
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* If a specific cache mode is not available, the closest available
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* one is returned instead (eg. writethru instead of writeback,
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* bypass instead of writethru).
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*/
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#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
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#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
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#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */
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#define XCHAL_CA_WRITEBACK_NOALLOC 4 /* cache enabled (write-back no-allocate) mode */
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#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
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#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */
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/*----------------------------------------------------------------------
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MMU
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----------------------------------------------------------------------*/
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/*
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* General notes on MMU parameters.
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*
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* Terminology:
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* ASID = address-space ID (acts as an "extension" of virtual addresses)
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* VPN = virtual page number
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* PPN = physical page number
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* CA = encoded cache attribute (access modes)
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* TLB = translation look-aside buffer (term is stretched somewhat here)
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* I = instruction (fetch accesses)
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* D = data (load and store accesses)
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* way = each TLB (ITLB and DTLB) consists of a number of "ways"
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* that simultaneously match the virtual address of an access;
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* a TLB successfully translates a virtual address if exactly
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* one way matches the vaddr; if none match, it is a miss;
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* if multiple match, one gets a "multihit" exception;
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* each way can be independently configured in terms of number of
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* entries, page sizes, which fields are writable or constant, etc.
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* set = group of contiguous ways with exactly identical parameters
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* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
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* from the page table and storing it in one of the auto-refill ways;
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* if this PTE load also misses, a miss exception is posted for s/w.
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* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
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* page arbitrarily under program control; it has a single entry,
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* is non-auto-refill (some other way(s) must be auto-refill),
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* all its fields (VPN, PPN, ASID, CA) are all writable, and it
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* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
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* restriction is that this be the only page size it supports).
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*
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* TLB way entries are virtually indexed.
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* TLB ways that support multiple page sizes:
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* - must have all writable VPN and PPN fields;
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* - can only use one page size at any given time (eg. setup at startup),
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* selected by the respective ITLBCFG or DTLBCFG special register,
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* whose bits n*4+3 .. n*4 index the list of page sizes for way n
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* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
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* this list may be sparse for auto-refill ways because auto-refill
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* ways have independent lists of supported page sizes sharing a
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* common encoding with PTE entries; the encoding is the index into
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* this list; unsupported sizes for a given way are zero in the list;
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* selecting unsupported sizes results in undefined hardware behaviour;
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* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
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*/
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#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
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#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
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#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
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#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
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#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
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#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
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/*** Instruction TLB: ***/
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#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
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#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
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#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
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#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
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/* Way set to which each way belongs: */
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#define XCHAL_ITLB_WAY0_SET 0
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/* Ways sets that are used by hardware auto-refill (ARF): */
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#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
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/* Way sets that are "min-wired" (see terminology comment above): */
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#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
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/* ITLB way set 0 (group of ways 0 thru 0): */
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#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
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#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
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#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
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#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
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#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
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#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
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#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
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#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
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#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
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#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
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2^PAGESZ_BITS entries in list, unsupported entries are zero */
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#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
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#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
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#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
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#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
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#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
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#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
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#define XCHAL_ITLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
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#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
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/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
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#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
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#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
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#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
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#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
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#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
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#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
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#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
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#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
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/* Reset PPN values for each entry of ITLB way set 0 (because SET0_PPN_RESET is non-zero): */
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#define XCHAL_ITLB_SET0_E0_PPN_RESET 0x00000000
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#define XCHAL_ITLB_SET0_E1_PPN_RESET 0x20000000
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#define XCHAL_ITLB_SET0_E2_PPN_RESET 0x40000000
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#define XCHAL_ITLB_SET0_E3_PPN_RESET 0x60000000
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#define XCHAL_ITLB_SET0_E4_PPN_RESET 0x80000000
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#define XCHAL_ITLB_SET0_E5_PPN_RESET 0xA0000000
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#define XCHAL_ITLB_SET0_E6_PPN_RESET 0xC0000000
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#define XCHAL_ITLB_SET0_E7_PPN_RESET 0xE0000000
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/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
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#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
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#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
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#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
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#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
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#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
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#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
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#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
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#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
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/*** Data TLB: ***/
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#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
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#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
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#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
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#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
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/* Way set to which each way belongs: */
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#define XCHAL_DTLB_WAY0_SET 0
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/* Ways sets that are used by hardware auto-refill (ARF): */
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#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
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/* Way sets that are "min-wired" (see terminology comment above): */
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#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
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/* DTLB way set 0 (group of ways 0 thru 0): */
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#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
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#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
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#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
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#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
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#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
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#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
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#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
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#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
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#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
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#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
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2^PAGESZ_BITS entries in list, unsupported entries are zero */
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#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
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#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
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#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
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#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
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#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
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#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
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#define XCHAL_DTLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
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#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
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/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
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#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
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#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
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#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
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#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
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#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
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#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
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#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
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#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
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/* Reset PPN values for each entry of DTLB way set 0 (because SET0_PPN_RESET is non-zero): */
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#define XCHAL_DTLB_SET0_E0_PPN_RESET 0x00000000
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#define XCHAL_DTLB_SET0_E1_PPN_RESET 0x20000000
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#define XCHAL_DTLB_SET0_E2_PPN_RESET 0x40000000
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#define XCHAL_DTLB_SET0_E3_PPN_RESET 0x60000000
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#define XCHAL_DTLB_SET0_E4_PPN_RESET 0x80000000
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#define XCHAL_DTLB_SET0_E5_PPN_RESET 0xA0000000
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#define XCHAL_DTLB_SET0_E6_PPN_RESET 0xC0000000
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#define XCHAL_DTLB_SET0_E7_PPN_RESET 0xE0000000
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/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
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#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
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#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
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#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
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#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
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#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
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#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
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#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
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#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
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#endif /* XTENSA_CONFIG_CORE_MATMAP_H */
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