qemu-e2k/target
Michael Clark a88365c199
RISC-V: Implement existential predicates for CSRs
CSR predicate functions are added to the CSR table.
mstatus.FS and counter enable checks are moved
to predicate functions and two new predicates are
added to check misa.S for s* CSRs and a new PMP
CPU feature for pmp* CSRs.

Processors that don't implement S-mode will trap
on access to s* CSRs and processors that don't
implement PMP will trap on accesses to pmp* CSRs.

PMP checks are disabled in riscv_cpu_handle_mmu_fault
when the PMP CPU feature is not present.

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-09 10:00:56 -08:00
..
alpha target/alpha: Fix user-only initialization of fpcr 2019-01-08 09:04:30 +10:00
arm target-arm queue: 2019-01-07 16:56:33 +00:00
cris
hppa vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
i386 qdev-props: remove errp from GlobalProperty 2019-01-07 16:18:42 +04:00
lm32
m68k target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTED 2018-11-01 12:12:24 +01:00
microblaze
mips target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions 2019-01-03 17:52:52 +01:00
moxie
nios2
openrisc vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
ppc Changes requirement for "vsubsbs" instruction 2018-12-21 09:29:12 +11:00
riscv RISC-V: Implement existential predicates for CSRs 2019-01-09 10:00:56 -08:00
s390x
sh4
sparc qdev-props: remove errp from GlobalProperty 2019-01-07 16:18:42 +04:00
tilegx
tricore target/tricore: use float32_is_denormal 2018-12-17 08:25:25 +00:00
unicore32
xtensa target/xtensa: drop num_[core_]regs from dc232b/dc233c configs 2018-11-20 12:20:41 -08:00