qemu-e2k/target/avr
Claudio Fontana 7827168471 cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.

Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.

This leaves just a NULL pointer in the cpu.h for the non-TCG builds.

This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-16-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05 10:24:15 -10:00
..
cpu-param.h
cpu-qom.h qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros 2020-09-18 14:12:32 -04:00
cpu.c cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
cpu.h target/avr: Add support for disassembling via option '-d in_asm' 2020-07-11 11:02:05 +02:00
disas.c meson: target 2020-08-21 06:30:35 -04:00
gdbstub.c target/avr: CPU class: Add GDB support 2020-07-10 17:58:32 +02:00
helper.c cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
helper.h target/avr: Add instruction helpers 2020-07-11 11:02:05 +02:00
insn.decode target/avr: Add instruction translation - MCU Control Instructions 2020-07-11 11:02:05 +02:00
machine.c migration: Replace migration's JSON writer by the general one 2020-12-19 10:39:16 +01:00
meson.build meson: target 2020-08-21 06:30:35 -04:00
translate.c meson: target 2020-08-21 06:30:35 -04:00