540635ba65
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3284 c046a42c-6fe2-441c-8c8c-71466251a162
1322 lines
43 KiB
C
1322 lines
43 KiB
C
/*
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* MIPS emulation helpers for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h>
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#include "exec.h"
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#define GETPC() (__builtin_return_address(0))
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/*****************************************************************************/
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/* Exceptions processing helpers */
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void do_raise_exception_err (uint32_t exception, int error_code)
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{
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#if 1
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if (logfile && exception < 0x100)
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fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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#endif
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env->exception_index = exception;
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env->error_code = error_code;
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T0 = 0;
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cpu_loop_exit();
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}
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void do_raise_exception (uint32_t exception)
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{
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do_raise_exception_err(exception, 0);
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}
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void do_restore_state (void *pc_ptr)
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{
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TranslationBlock *tb;
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unsigned long pc = (unsigned long) pc_ptr;
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tb = tb_find_pc (pc);
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cpu_restore_state (tb, env, pc, NULL);
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}
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void do_raise_exception_direct_err (uint32_t exception, int error_code)
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{
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do_restore_state (GETPC ());
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do_raise_exception_err (exception, error_code);
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}
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void do_raise_exception_direct (uint32_t exception)
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{
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do_raise_exception_direct_err (exception, 0);
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}
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#define MEMSUFFIX _raw
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#include "op_helper_mem.c"
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_helper_mem.c"
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_helper_mem.c"
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#undef MEMSUFFIX
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#endif
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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/* Those might call libgcc functions. */
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void do_dsll (void)
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{
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T0 = T0 << T1;
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}
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void do_dsll32 (void)
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{
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T0 = T0 << (T1 + 32);
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}
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void do_dsra (void)
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{
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T0 = (int64_t)T0 >> T1;
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}
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void do_dsra32 (void)
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{
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T0 = (int64_t)T0 >> (T1 + 32);
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}
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void do_dsrl (void)
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{
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T0 = T0 >> T1;
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}
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void do_dsrl32 (void)
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{
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T0 = T0 >> (T1 + 32);
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}
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void do_drotr (void)
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{
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target_ulong tmp;
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if (T1) {
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tmp = T0 << (0x40 - T1);
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T0 = (T0 >> T1) | tmp;
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}
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}
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void do_drotr32 (void)
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{
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target_ulong tmp;
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if (T1) {
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tmp = T0 << (0x40 - (32 + T1));
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T0 = (T0 >> (32 + T1)) | tmp;
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}
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}
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void do_dsllv (void)
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{
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T0 = T1 << (T0 & 0x3F);
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}
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void do_dsrav (void)
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{
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T0 = (int64_t)T1 >> (T0 & 0x3F);
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}
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void do_dsrlv (void)
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{
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T0 = T1 >> (T0 & 0x3F);
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}
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void do_drotrv (void)
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{
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target_ulong tmp;
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T0 &= 0x3F;
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if (T0) {
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tmp = T1 << (0x40 - T0);
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T0 = (T1 >> T0) | tmp;
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} else
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T0 = T1;
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}
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#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
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#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
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/* 64 bits arithmetic for 32 bits hosts */
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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static inline uint64_t get_HILO (void)
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{
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return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
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}
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static inline void set_HILO (uint64_t HILO)
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{
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env->LO[0][env->current_tc] = (int32_t)HILO;
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env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
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}
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void do_mult (void)
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{
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set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
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}
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void do_multu (void)
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{
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set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
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}
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void do_madd (void)
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{
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int64_t tmp;
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tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
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set_HILO((int64_t)get_HILO() + tmp);
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}
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void do_maddu (void)
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{
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uint64_t tmp;
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tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
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set_HILO(get_HILO() + tmp);
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}
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void do_msub (void)
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{
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int64_t tmp;
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tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
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set_HILO((int64_t)get_HILO() - tmp);
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}
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void do_msubu (void)
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{
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uint64_t tmp;
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tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
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set_HILO(get_HILO() - tmp);
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}
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#endif
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#if HOST_LONG_BITS < 64
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void do_div (void)
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{
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/* 64bit datatypes because we may see overflow/underflow. */
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if (T1 != 0) {
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env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
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env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
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}
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}
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#endif
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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void do_ddiv (void)
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{
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if (T1 != 0) {
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lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
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env->LO[0][env->current_tc] = res.quot;
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env->HI[0][env->current_tc] = res.rem;
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}
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}
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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void do_ddivu (void)
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{
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if (T1 != 0) {
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env->LO[0][env->current_tc] = T0 / T1;
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env->HI[0][env->current_tc] = T0 % T1;
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}
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}
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#endif
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#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
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#if defined(CONFIG_USER_ONLY)
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void do_mfc0_random (void)
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{
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cpu_abort(env, "mfc0 random\n");
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}
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void do_mfc0_count (void)
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{
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cpu_abort(env, "mfc0 count\n");
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}
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void cpu_mips_store_count(CPUState *env, uint32_t value)
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{
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cpu_abort(env, "mtc0 count\n");
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}
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void cpu_mips_store_compare(CPUState *env, uint32_t value)
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{
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cpu_abort(env, "mtc0 compare\n");
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}
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void cpu_mips_start_count(CPUState *env)
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{
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cpu_abort(env, "start count\n");
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}
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void cpu_mips_stop_count(CPUState *env)
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{
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cpu_abort(env, "stop count\n");
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}
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void cpu_mips_update_irq(CPUState *env)
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{
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cpu_abort(env, "mtc0 status / mtc0 cause\n");
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}
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void do_mtc0_status_debug(uint32_t old, uint32_t val)
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{
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cpu_abort(env, "mtc0 status debug\n");
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}
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void do_mtc0_status_irqraise_debug (void)
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{
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cpu_abort(env, "mtc0 status irqraise debug\n");
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}
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void cpu_mips_tlb_flush (CPUState *env, int flush_global)
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{
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cpu_abort(env, "mips_tlb_flush\n");
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}
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#else
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/* CP0 helpers */
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void do_mfc0_random (void)
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{
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T0 = (int32_t)cpu_mips_get_random(env);
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}
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void do_mfc0_count (void)
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{
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T0 = (int32_t)cpu_mips_get_count(env);
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}
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void do_mtc0_status_debug(uint32_t old, uint32_t val)
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{
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fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
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old, old & env->CP0_Cause & CP0Ca_IP_mask,
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val, val & env->CP0_Cause & CP0Ca_IP_mask,
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env->CP0_Cause);
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(env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
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: fputs("\n", logfile);
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}
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void do_mtc0_status_irqraise_debug(void)
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{
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fprintf(logfile, "Raise pending IRQs\n");
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}
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void fpu_handle_exception(void)
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{
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#ifdef CONFIG_SOFTFLOAT
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int flags = get_float_exception_flags(&env->fpu->fp_status);
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unsigned int cpuflags = 0, enable, cause = 0;
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enable = GET_FP_ENABLE(env->fpu->fcr31);
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/* determine current flags */
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if (flags & float_flag_invalid) {
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cpuflags |= FP_INVALID;
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cause |= FP_INVALID & enable;
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}
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if (flags & float_flag_divbyzero) {
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cpuflags |= FP_DIV0;
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cause |= FP_DIV0 & enable;
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}
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if (flags & float_flag_overflow) {
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cpuflags |= FP_OVERFLOW;
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cause |= FP_OVERFLOW & enable;
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}
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if (flags & float_flag_underflow) {
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cpuflags |= FP_UNDERFLOW;
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cause |= FP_UNDERFLOW & enable;
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}
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if (flags & float_flag_inexact) {
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cpuflags |= FP_INEXACT;
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cause |= FP_INEXACT & enable;
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}
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SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
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SET_FP_CAUSE(env->fpu->fcr31, cause);
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#else
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SET_FP_FLAGS(env->fpu->fcr31, 0);
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SET_FP_CAUSE(env->fpu->fcr31, 0);
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#endif
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}
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/* TLB management */
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void cpu_mips_tlb_flush (CPUState *env, int flush_global)
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{
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/* Flush qemu's TLB and discard all shadowed entries. */
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tlb_flush (env, flush_global);
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env->tlb->tlb_in_use = env->tlb->nb_tlb;
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}
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static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
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{
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/* Discard entries from env->tlb[first] onwards. */
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while (env->tlb->tlb_in_use > first) {
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r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
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}
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}
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static void r4k_fill_tlb (int idx)
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{
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r4k_tlb_t *tlb;
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/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
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tlb = &env->tlb->mmu.r4k.tlb[idx];
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tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
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#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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tlb->VPN &= env->SEGMask;
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#endif
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tlb->ASID = env->CP0_EntryHi & 0xFF;
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tlb->PageMask = env->CP0_PageMask;
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tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
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tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
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tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
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tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
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tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
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tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
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tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
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tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
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tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
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}
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void r4k_do_tlbwi (void)
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{
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/* Discard cached TLB entries. We could avoid doing this if the
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tlbwi is just upgrading access permissions on the current entry;
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that might be a further win. */
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r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
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r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
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r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
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}
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void r4k_do_tlbwr (void)
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{
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int r = cpu_mips_get_random(env);
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r4k_invalidate_tlb(env, r, 1);
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r4k_fill_tlb(r);
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}
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void r4k_do_tlbp (void)
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{
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r4k_tlb_t *tlb;
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target_ulong mask;
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target_ulong tag;
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target_ulong VPN;
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uint8_t ASID;
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int i;
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ASID = env->CP0_EntryHi & 0xFF;
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for (i = 0; i < env->tlb->nb_tlb; i++) {
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tlb = &env->tlb->mmu.r4k.tlb[i];
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/* 1k pages are not supported. */
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mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
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tag = env->CP0_EntryHi & ~mask;
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VPN = tlb->VPN & ~mask;
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/* Check ASID, virtual page number & size */
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if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
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/* TLB match */
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env->CP0_Index = i;
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break;
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}
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}
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if (i == env->tlb->nb_tlb) {
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/* No match. Discard any shadow entries, if any of them match. */
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for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
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tlb = &env->tlb->mmu.r4k.tlb[i];
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/* 1k pages are not supported. */
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mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
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tag = env->CP0_EntryHi & ~mask;
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VPN = tlb->VPN & ~mask;
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/* Check ASID, virtual page number & size */
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if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
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r4k_mips_tlb_flush_extra (env, i);
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break;
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}
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}
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env->CP0_Index |= 0x80000000;
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}
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}
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void r4k_do_tlbr (void)
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{
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r4k_tlb_t *tlb;
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uint8_t ASID;
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ASID = env->CP0_EntryHi & 0xFF;
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tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
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/* If this will change the current ASID, flush qemu's TLB. */
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if (ASID != tlb->ASID)
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cpu_mips_tlb_flush (env, 1);
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r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
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env->CP0_EntryHi = tlb->VPN | tlb->ASID;
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env->CP0_PageMask = tlb->PageMask;
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env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
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(tlb->C0 << 3) | (tlb->PFN[0] >> 6);
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env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
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(tlb->C1 << 3) | (tlb->PFN[1] >> 6);
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}
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#endif /* !CONFIG_USER_ONLY */
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void dump_ldst (const unsigned char *func)
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{
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if (loglevel)
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fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
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}
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void dump_sc (void)
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{
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if (loglevel) {
|
|
fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
|
|
T1, T0, env->CP0_LLAddr);
|
|
}
|
|
}
|
|
|
|
void debug_pre_eret (void)
|
|
{
|
|
fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
|
|
env->PC[env->current_tc], env->CP0_EPC);
|
|
if (env->CP0_Status & (1 << CP0St_ERL))
|
|
fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
|
if (env->hflags & MIPS_HFLAG_DM)
|
|
fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
|
fputs("\n", logfile);
|
|
}
|
|
|
|
void debug_post_eret (void)
|
|
{
|
|
fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
|
|
env->PC[env->current_tc], env->CP0_EPC);
|
|
if (env->CP0_Status & (1 << CP0St_ERL))
|
|
fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
|
|
if (env->hflags & MIPS_HFLAG_DM)
|
|
fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
|
|
if (env->hflags & MIPS_HFLAG_UM)
|
|
fputs(", UM\n", logfile);
|
|
else
|
|
fputs("\n", logfile);
|
|
}
|
|
|
|
void do_pmon (int function)
|
|
{
|
|
function /= 2;
|
|
switch (function) {
|
|
case 2: /* TODO: char inbyte(int waitflag); */
|
|
if (env->gpr[4][env->current_tc] == 0)
|
|
env->gpr[2][env->current_tc] = -1;
|
|
/* Fall through */
|
|
case 11: /* TODO: char inbyte (void); */
|
|
env->gpr[2][env->current_tc] = -1;
|
|
break;
|
|
case 3:
|
|
case 12:
|
|
printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF));
|
|
break;
|
|
case 17:
|
|
break;
|
|
case 158:
|
|
{
|
|
unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc];
|
|
printf("%s", fmt);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
|
|
|
|
#define MMUSUFFIX _mmu
|
|
#define ALIGNED_ONLY
|
|
|
|
#define SHIFT 0
|
|
#include "softmmu_template.h"
|
|
|
|
#define SHIFT 1
|
|
#include "softmmu_template.h"
|
|
|
|
#define SHIFT 2
|
|
#include "softmmu_template.h"
|
|
|
|
#define SHIFT 3
|
|
#include "softmmu_template.h"
|
|
|
|
static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
|
|
{
|
|
env->CP0_BadVAddr = addr;
|
|
do_restore_state (retaddr);
|
|
do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
|
}
|
|
|
|
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
|
|
{
|
|
TranslationBlock *tb;
|
|
CPUState *saved_env;
|
|
unsigned long pc;
|
|
int ret;
|
|
|
|
/* XXX: hack to restore env in all cases, even if not called from
|
|
generated code */
|
|
saved_env = env;
|
|
env = cpu_single_env;
|
|
ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
|
if (ret) {
|
|
if (retaddr) {
|
|
/* now we have a real cpu fault */
|
|
pc = (unsigned long)retaddr;
|
|
tb = tb_find_pc(pc);
|
|
if (tb) {
|
|
/* the PC is inside the translated code. It means that we have
|
|
a virtual CPU fault */
|
|
cpu_restore_state(tb, env, pc, NULL);
|
|
}
|
|
}
|
|
do_raise_exception_err(env->exception_index, env->error_code);
|
|
}
|
|
env = saved_env;
|
|
}
|
|
|
|
#endif
|
|
|
|
/* Complex FPU operations which may need stack space. */
|
|
|
|
#define FLOAT_SIGN32 (1 << 31)
|
|
#define FLOAT_SIGN64 (1ULL << 63)
|
|
#define FLOAT_ONE32 (0x3f8 << 20)
|
|
#define FLOAT_ONE64 (0x3ffULL << 52)
|
|
#define FLOAT_TWO32 (1 << 30)
|
|
#define FLOAT_TWO64 (1ULL << 62)
|
|
#define FLOAT_QNAN32 0x7fbfffff
|
|
#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
|
|
#define FLOAT_SNAN32 0x7fffffff
|
|
#define FLOAT_SNAN64 0x7fffffffffffffffULL
|
|
|
|
/* convert MIPS rounding mode in FCR31 to IEEE library */
|
|
unsigned int ieee_rm[] = {
|
|
float_round_nearest_even,
|
|
float_round_to_zero,
|
|
float_round_up,
|
|
float_round_down
|
|
};
|
|
|
|
#define RESTORE_ROUNDING_MODE \
|
|
set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
|
|
|
|
void do_cfc1 (int reg)
|
|
{
|
|
switch (reg) {
|
|
case 0:
|
|
T0 = (int32_t)env->fpu->fcr0;
|
|
break;
|
|
case 25:
|
|
T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
|
|
break;
|
|
case 26:
|
|
T0 = env->fpu->fcr31 & 0x0003f07c;
|
|
break;
|
|
case 28:
|
|
T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
|
|
break;
|
|
default:
|
|
T0 = (int32_t)env->fpu->fcr31;
|
|
break;
|
|
}
|
|
}
|
|
|
|
void do_ctc1 (int reg)
|
|
{
|
|
switch(reg) {
|
|
case 25:
|
|
if (T0 & 0xffffff00)
|
|
return;
|
|
env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
|
|
((T0 & 0x1) << 23);
|
|
break;
|
|
case 26:
|
|
if (T0 & 0x007c0000)
|
|
return;
|
|
env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
|
|
break;
|
|
case 28:
|
|
if (T0 & 0x007c0000)
|
|
return;
|
|
env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
|
|
((T0 & 0x4) << 22);
|
|
break;
|
|
case 31:
|
|
if (T0 & 0x007c0000)
|
|
return;
|
|
env->fpu->fcr31 = T0;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
/* set rounding mode */
|
|
RESTORE_ROUNDING_MODE;
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
|
|
do_raise_exception(EXCP_FPE);
|
|
}
|
|
|
|
inline char ieee_ex_to_mips(char xcpt)
|
|
{
|
|
return (xcpt & float_flag_inexact) >> 5 |
|
|
(xcpt & float_flag_underflow) >> 3 |
|
|
(xcpt & float_flag_overflow) >> 1 |
|
|
(xcpt & float_flag_divbyzero) << 1 |
|
|
(xcpt & float_flag_invalid) << 4;
|
|
}
|
|
|
|
inline char mips_ex_to_ieee(char xcpt)
|
|
{
|
|
return (xcpt & FP_INEXACT) << 5 |
|
|
(xcpt & FP_UNDERFLOW) << 3 |
|
|
(xcpt & FP_OVERFLOW) << 1 |
|
|
(xcpt & FP_DIV0) >> 1 |
|
|
(xcpt & FP_INVALID) >> 4;
|
|
}
|
|
|
|
inline void update_fcr31(void)
|
|
{
|
|
int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
|
|
|
|
SET_FP_CAUSE(env->fpu->fcr31, tmp);
|
|
if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
|
|
do_raise_exception(EXCP_FPE);
|
|
else
|
|
UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
|
|
}
|
|
|
|
#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
|
|
|
|
FLOAT_OP(cvtd, s)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(cvtd, w)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(cvtd, l)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(cvtl, d)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
FLOAT_OP(cvtl, s)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
|
|
FLOAT_OP(cvtps, pw)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
|
|
FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(cvtpw, ps)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
FLOAT_OP(cvts, d)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(cvts, w)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(cvts, l)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(cvts, pl)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
WT2 = WT0;
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(cvts, pu)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
WT2 = WTH0;
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(cvtw, s)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
FLOAT_OP(cvtw, d)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
|
|
FLOAT_OP(roundl, d)
|
|
{
|
|
set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
|
|
DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
FLOAT_OP(roundl, s)
|
|
{
|
|
set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
|
|
DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
FLOAT_OP(roundw, d)
|
|
{
|
|
set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
|
|
WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
FLOAT_OP(roundw, s)
|
|
{
|
|
set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
|
|
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
|
|
FLOAT_OP(truncl, d)
|
|
{
|
|
DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
FLOAT_OP(truncl, s)
|
|
{
|
|
DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
FLOAT_OP(truncw, d)
|
|
{
|
|
WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
FLOAT_OP(truncw, s)
|
|
{
|
|
WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
|
|
FLOAT_OP(ceill, d)
|
|
{
|
|
set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
|
|
DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
FLOAT_OP(ceill, s)
|
|
{
|
|
set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
|
|
DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
FLOAT_OP(ceilw, d)
|
|
{
|
|
set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
|
|
WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
FLOAT_OP(ceilw, s)
|
|
{
|
|
set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
|
|
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
|
|
FLOAT_OP(floorl, d)
|
|
{
|
|
set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
|
|
DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
FLOAT_OP(floorl, s)
|
|
{
|
|
set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
|
|
DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
DT2 = FLOAT_SNAN64;
|
|
}
|
|
FLOAT_OP(floorw, d)
|
|
{
|
|
set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
|
|
WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
FLOAT_OP(floorw, s)
|
|
{
|
|
set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
|
|
WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
|
|
RESTORE_ROUNDING_MODE;
|
|
update_fcr31();
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
|
|
WT2 = FLOAT_SNAN32;
|
|
}
|
|
|
|
/* MIPS specific unary operations */
|
|
FLOAT_OP(recip, d)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(recip, s)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
|
|
FLOAT_OP(rsqrt, d)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
|
|
FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(rsqrt, s)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
|
|
FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
|
|
FLOAT_OP(recip1, d)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(recip1, s)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(recip1, ps)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
|
|
FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
|
|
FLOAT_OP(rsqrt1, d)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
|
|
FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(rsqrt1, s)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
|
|
FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(rsqrt1, ps)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
|
|
FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
|
|
FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
|
|
FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
|
|
/* binary operations */
|
|
#define FLOAT_BINOP(name) \
|
|
FLOAT_OP(name, d) \
|
|
{ \
|
|
set_float_exception_flags(0, &env->fpu->fp_status); \
|
|
FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
|
|
update_fcr31(); \
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
|
FDT2 = FLOAT_QNAN64; \
|
|
} \
|
|
FLOAT_OP(name, s) \
|
|
{ \
|
|
set_float_exception_flags(0, &env->fpu->fp_status); \
|
|
FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
|
|
update_fcr31(); \
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
|
|
FST2 = FLOAT_QNAN32; \
|
|
} \
|
|
FLOAT_OP(name, ps) \
|
|
{ \
|
|
set_float_exception_flags(0, &env->fpu->fp_status); \
|
|
FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
|
|
FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
|
|
update_fcr31(); \
|
|
if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
|
|
FST2 = FLOAT_QNAN32; \
|
|
FSTH2 = FLOAT_QNAN32; \
|
|
} \
|
|
}
|
|
FLOAT_BINOP(add)
|
|
FLOAT_BINOP(sub)
|
|
FLOAT_BINOP(mul)
|
|
FLOAT_BINOP(div)
|
|
#undef FLOAT_BINOP
|
|
|
|
/* MIPS specific binary operations */
|
|
FLOAT_OP(recip2, d)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
|
|
FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(recip2, s)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
|
|
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(recip2, ps)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
|
|
FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
|
|
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
update_fcr31();
|
|
}
|
|
|
|
FLOAT_OP(rsqrt2, d)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
|
|
FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
|
|
FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(rsqrt2, s)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
|
|
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
|
|
FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
update_fcr31();
|
|
}
|
|
FLOAT_OP(rsqrt2, ps)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
|
|
FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
|
|
FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
|
|
FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
|
|
FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
|
|
update_fcr31();
|
|
}
|
|
|
|
FLOAT_OP(addr, ps)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
|
|
FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
|
|
FLOAT_OP(mulr, ps)
|
|
{
|
|
set_float_exception_flags(0, &env->fpu->fp_status);
|
|
FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
|
|
FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
|
|
update_fcr31();
|
|
}
|
|
|
|
/* compare operations */
|
|
#define FOP_COND_D(op, cond) \
|
|
void do_cmp_d_ ## op (long cc) \
|
|
{ \
|
|
int c = cond; \
|
|
update_fcr31(); \
|
|
if (c) \
|
|
SET_FP_COND(cc, env->fpu); \
|
|
else \
|
|
CLEAR_FP_COND(cc, env->fpu); \
|
|
} \
|
|
void do_cmpabs_d_ ## op (long cc) \
|
|
{ \
|
|
int c; \
|
|
FDT0 &= ~FLOAT_SIGN64; \
|
|
FDT1 &= ~FLOAT_SIGN64; \
|
|
c = cond; \
|
|
update_fcr31(); \
|
|
if (c) \
|
|
SET_FP_COND(cc, env->fpu); \
|
|
else \
|
|
CLEAR_FP_COND(cc, env->fpu); \
|
|
}
|
|
|
|
int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
|
|
{
|
|
if (float64_is_signaling_nan(a) ||
|
|
float64_is_signaling_nan(b) ||
|
|
(sig && (float64_is_nan(a) || float64_is_nan(b)))) {
|
|
float_raise(float_flag_invalid, status);
|
|
return 1;
|
|
} else if (float64_is_nan(a) || float64_is_nan(b)) {
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* NOTE: the comma operator will make "cond" to eval to false,
|
|
* but float*_is_unordered() is still called. */
|
|
FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
|
|
FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
|
|
FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
|
/* NOTE: the comma operator will make "cond" to eval to false,
|
|
* but float*_is_unordered() is still called. */
|
|
FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
|
|
FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
|
|
FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
|
FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
|
|
|
|
#define FOP_COND_S(op, cond) \
|
|
void do_cmp_s_ ## op (long cc) \
|
|
{ \
|
|
int c = cond; \
|
|
update_fcr31(); \
|
|
if (c) \
|
|
SET_FP_COND(cc, env->fpu); \
|
|
else \
|
|
CLEAR_FP_COND(cc, env->fpu); \
|
|
} \
|
|
void do_cmpabs_s_ ## op (long cc) \
|
|
{ \
|
|
int c; \
|
|
FST0 &= ~FLOAT_SIGN32; \
|
|
FST1 &= ~FLOAT_SIGN32; \
|
|
c = cond; \
|
|
update_fcr31(); \
|
|
if (c) \
|
|
SET_FP_COND(cc, env->fpu); \
|
|
else \
|
|
CLEAR_FP_COND(cc, env->fpu); \
|
|
}
|
|
|
|
flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
|
|
{
|
|
if (float32_is_signaling_nan(a) ||
|
|
float32_is_signaling_nan(b) ||
|
|
(sig && (float32_is_nan(a) || float32_is_nan(b)))) {
|
|
float_raise(float_flag_invalid, status);
|
|
return 1;
|
|
} else if (float32_is_nan(a) || float32_is_nan(b)) {
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/* NOTE: the comma operator will make "cond" to eval to false,
|
|
* but float*_is_unordered() is still called. */
|
|
FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
|
|
FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
|
|
FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
|
/* NOTE: the comma operator will make "cond" to eval to false,
|
|
* but float*_is_unordered() is still called. */
|
|
FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
|
|
FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
|
|
FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
|
|
FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
|
|
|
|
#define FOP_COND_PS(op, condl, condh) \
|
|
void do_cmp_ps_ ## op (long cc) \
|
|
{ \
|
|
int cl = condl; \
|
|
int ch = condh; \
|
|
update_fcr31(); \
|
|
if (cl) \
|
|
SET_FP_COND(cc, env->fpu); \
|
|
else \
|
|
CLEAR_FP_COND(cc, env->fpu); \
|
|
if (ch) \
|
|
SET_FP_COND(cc + 1, env->fpu); \
|
|
else \
|
|
CLEAR_FP_COND(cc + 1, env->fpu); \
|
|
} \
|
|
void do_cmpabs_ps_ ## op (long cc) \
|
|
{ \
|
|
int cl, ch; \
|
|
FST0 &= ~FLOAT_SIGN32; \
|
|
FSTH0 &= ~FLOAT_SIGN32; \
|
|
FST1 &= ~FLOAT_SIGN32; \
|
|
FSTH1 &= ~FLOAT_SIGN32; \
|
|
cl = condl; \
|
|
ch = condh; \
|
|
update_fcr31(); \
|
|
if (cl) \
|
|
SET_FP_COND(cc, env->fpu); \
|
|
else \
|
|
CLEAR_FP_COND(cc, env->fpu); \
|
|
if (ch) \
|
|
SET_FP_COND(cc + 1, env->fpu); \
|
|
else \
|
|
CLEAR_FP_COND(cc + 1, env->fpu); \
|
|
}
|
|
|
|
/* NOTE: the comma operator will make "cond" to eval to false,
|
|
* but float*_is_unordered() is still called. */
|
|
FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
|
|
(float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
|
|
FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
|
|
float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
|
|
FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
|
!float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
|
float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
|
!float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
|
float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
|
!float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
|
float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
/* NOTE: the comma operator will make "cond" to eval to false,
|
|
* but float*_is_unordered() is still called. */
|
|
FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
|
|
(float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
|
|
FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
|
|
float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
|
|
FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
|
|
!float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
|
|
float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
|
|
!float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
|
|
float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
|
|
!float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|
|
FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
|
|
float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
|