5c4537bded
daa2369 "spapr_pci: Add a 64-bit MMIO window" subtly broke migration
from qemu-2.7 to the current version. It split the device's MMIO
window into two pieces for 32-bit and 64-bit MMIO.
The patch included backwards compatibility code to convert the old
property into the new format. However, the property value was also
transferred in the migration stream and compared with a (probably
unwise) VMSTATE_EQUAL. So, the "raw" value from 2.7 is compared to
the new style converted value from (pre-)2.8 giving a mismatch and
migration failure.
Along with the actual field that caused the breakage, there are
several other ill-advised VMSTATE_EQUAL()s. To fix forwards
migration, we read the values in the stream into scratch variables and
ignore them, instead of comparing for equality. To fix backwards
migration, we populate those scratch variables in pre_save() with
adjusted values to match the old behaviour.
To permit the eventual possibility of removing this cruft from the
stream, we only include these compatibility fields if a new
'pre-2.8-migration' property is set. We clear it on the pseries-2.8
machine type, which obviously can't be migrated backwards, but set it
on earlier machine type versions.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
164 lines
4.8 KiB
C
164 lines
4.8 KiB
C
/*
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* QEMU SPAPR PCI BUS definitions
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*
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* Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PCI_HOST_SPAPR_H
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#define PCI_HOST_SPAPR_H
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#include "hw/ppc/spapr.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/xics.h"
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#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
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#define SPAPR_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
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#define SPAPR_PCI_DMA_MAX_WINDOWS 2
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typedef struct sPAPRPHBState sPAPRPHBState;
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typedef struct spapr_pci_msi {
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uint32_t first_irq;
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uint32_t num;
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} spapr_pci_msi;
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typedef struct spapr_pci_msi_mig {
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uint32_t key;
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spapr_pci_msi value;
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} spapr_pci_msi_mig;
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struct sPAPRPHBState {
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PCIHostState parent_obj;
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uint32_t index;
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uint64_t buid;
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char *dtbusname;
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bool dr_enabled;
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MemoryRegion memspace, iospace;
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hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
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uint64_t mem64_win_pciaddr;
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hwaddr io_win_addr, io_win_size;
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MemoryRegion mem32window, mem64window, iowindow, msiwindow;
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uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
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hwaddr dma_win_addr, dma_win_size;
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AddressSpace iommu_as;
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MemoryRegion iommu_root;
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struct spapr_pci_lsi {
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uint32_t irq;
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} lsi_table[PCI_NUM_PINS];
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GHashTable *msi;
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/* Temporary cache for migration purposes */
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int32_t msi_devs_num;
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spapr_pci_msi_mig *msi_devs;
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QLIST_ENTRY(sPAPRPHBState) list;
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bool ddw_enabled;
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uint64_t page_size_mask;
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uint64_t dma64_win_addr;
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uint32_t numa_node;
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/* Fields for migration compatibility hacks */
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bool pre_2_8_migration;
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uint32_t mig_liobn;
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hwaddr mig_mem_win_addr, mig_mem_win_size;
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hwaddr mig_io_win_addr, mig_io_win_size;
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};
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#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
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#define SPAPR_PCI_MEM32_WIN_SIZE \
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((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
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#define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */
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/* Without manual configuration, all PCI outbound windows will be
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* within this range */
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#define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */
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#define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */
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#define SPAPR_PCI_2_7_MMIO_WIN_SIZE 0xf80000000
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#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
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static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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return xics_get_qirq(spapr->xics, phb->lsi_table[pin].irq);
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}
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PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
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int spapr_populate_pci_dt(sPAPRPHBState *phb,
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uint32_t xics_phandle,
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void *fdt);
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void spapr_pci_rtas_init(void);
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sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
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PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
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uint32_t config_addr);
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/* VFIO EEH hooks */
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#ifdef CONFIG_LINUX
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bool spapr_phb_eeh_available(sPAPRPHBState *sphb);
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int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
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unsigned int addr, int option);
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int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state);
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int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option);
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int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb);
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void spapr_phb_vfio_reset(DeviceState *qdev);
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#else
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static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb)
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{
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return false;
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}
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static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
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unsigned int addr, int option)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb,
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int *state)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
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{
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return RTAS_OUT_HW_ERROR;
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}
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static inline void spapr_phb_vfio_reset(DeviceState *qdev)
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{
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}
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#endif
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void spapr_phb_dma_reset(sPAPRPHBState *sphb);
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#endif /* PCI_HOST_SPAPR_H */
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