Claudio Fontana 8191d36841 icount: rename functions to be consistent with the module name ... Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2020-10-05 16:41:22 +02:00
..
insn_trans	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
cpu_bits.h	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
cpu_helper.c	qemu/atomic.h: rename atomic_ to qatomic_	2020-09-23 16:07:44 +01:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Set instance_align on RISCVCPU TypeInfo	2020-09-18 13:59:51 -04:00
cpu.h	qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros	2020-09-18 14:12:32 -04:00
csr.c	icount: rename functions to be consistent with the module name	2020-10-05 16:41:22 +02:00
fpu_helper.c
gdbstub.c
helper.h	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
insn32.decode	target/riscv: Allow generating hlv/hlvx/hsv instructions	2020-08-25 09:11:35 -07:00
instmap.h
internals.h
meson.build
monitor.c
op_helper.c	target/riscv: Support the Virtual Instruction fault	2020-08-25 09:11:36 -07:00
pmp.c
pmp.h
trace-events	trace-events: Fix attribution of trace points to source	2020-09-09 17:17:58 +01:00
trace.h
translate.c	target/riscv: Update the Hypervisor trap return/entry	2020-08-25 09:11:36 -07:00
vector_helper.c	softfloat: Implement the full set of comparisons for float16	2020-08-28 10:48:07 -07:00