2e8f85189d
The MC146818 RTC was incorrectly added to the i82378 chipset in commita04ff94097. In the next commit (506b7ddf88) the PReP machine use the i82378. Since the MC146818 is specific to the PReP machine, move its use there. Fixes:a04ff94097Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190505152839.18650-3-philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
150 lines
3.9 KiB
C
150 lines
3.9 KiB
C
/*
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* QEMU Intel i82378 emulation (PCI to ISA bridge)
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*
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* Copyright (c) 2010-2011 Hervé Poussineau
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/i386/pc.h"
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#include "hw/timer/i8254.h"
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#include "hw/audio/pcspk.h"
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#define TYPE_I82378 "i82378"
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#define I82378(obj) \
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OBJECT_CHECK(I82378State, (obj), TYPE_I82378)
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typedef struct I82378State {
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PCIDevice parent_obj;
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qemu_irq out[2];
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qemu_irq *i8259;
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MemoryRegion io;
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} I82378State;
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static const VMStateDescription vmstate_i82378 = {
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.name = "pci-i82378",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, I82378State),
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VMSTATE_END_OF_LIST()
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},
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};
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static void i82378_request_out0_irq(void *opaque, int irq, int level)
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{
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I82378State *s = opaque;
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qemu_set_irq(s->out[0], level);
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}
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static void i82378_request_pic_irq(void *opaque, int irq, int level)
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{
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DeviceState *dev = opaque;
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I82378State *s = I82378(dev);
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qemu_set_irq(s->i8259[irq], level);
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}
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static void i82378_realize(PCIDevice *pci, Error **errp)
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{
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DeviceState *dev = DEVICE(pci);
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I82378State *s = I82378(dev);
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uint8_t *pci_conf;
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ISABus *isabus;
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ISADevice *isa;
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pci_conf = pci->config;
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pci_set_word(pci_conf + PCI_COMMAND,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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pci_set_word(pci_conf + PCI_STATUS,
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PCI_STATUS_DEVSEL_MEDIUM);
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pci_config_set_interrupt_pin(pci_conf, 1); /* interrupt pin 0 */
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isabus = isa_bus_new(dev, get_system_memory(),
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pci_address_space_io(pci), errp);
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if (!isabus) {
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return;
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}
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/* This device has:
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2 82C59 (irq)
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1 82C54 (pit)
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2 82C37 (dma)
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NMI
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Utility Bus Support Registers
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All devices accept byte access only, except timer
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*/
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/* 2 82C59 (irq) */
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s->i8259 = i8259_init(isabus,
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qemu_allocate_irq(i82378_request_out0_irq, s, 0));
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isa_bus_irqs(isabus, s->i8259);
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/* 1 82C54 (pit) */
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isa = i8254_pit_init(isabus, 0x40, 0, NULL);
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/* speaker */
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pcspk_init(isabus, isa);
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/* 2 82C37 (dma) */
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isa = isa_create_simple(isabus, "i82374");
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}
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static void i82378_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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I82378State *s = I82378(obj);
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qdev_init_gpio_out(dev, s->out, 1);
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qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
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}
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static void i82378_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = i82378_realize;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82378;
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k->revision = 0x03;
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k->class_id = PCI_CLASS_BRIDGE_ISA;
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dc->vmsd = &vmstate_i82378;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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}
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static const TypeInfo i82378_type_info = {
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.name = TYPE_I82378,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(I82378State),
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.instance_init = i82378_init,
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.class_init = i82378_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void i82378_register_types(void)
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{
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type_register_static(&i82378_type_info);
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}
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type_init(i82378_register_types)
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