1234 lines
39 KiB
C
1234 lines
39 KiB
C
/*
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* QEMU e1000 emulation
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*
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* Software developer's manual:
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* http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
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*
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* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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* Copyright (c) 2008 Qumranet
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* Based on work done by:
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* Copyright (c) 2007 Dan Aloni
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* Copyright (c) 2004 Antony T Curtis
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "net.h"
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#include "net/checksum.h"
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#include "loader.h"
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#include "sysemu.h"
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#include "dma.h"
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#include "e1000_hw.h"
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#define E1000_DEBUG
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#ifdef E1000_DEBUG
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enum {
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DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
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DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
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DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
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DEBUG_RXFILTER, DEBUG_NOTYET,
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};
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#define DBGBIT(x) (1<<DEBUG_##x)
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static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
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#define DBGOUT(what, fmt, ...) do { \
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if (debugflags & DBGBIT(what)) \
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fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
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} while (0)
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#else
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#define DBGOUT(what, fmt, ...) do {} while (0)
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#endif
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#define IOPORT_SIZE 0x40
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#define PNPMMIO_SIZE 0x20000
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#define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
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/*
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* HW models:
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* E1000_DEV_ID_82540EM works with Windows and Linux
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* E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
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* appears to perform better than 82540EM, but breaks with Linux 2.6.18
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* E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
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* Others never tested
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*/
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enum { E1000_DEVID = E1000_DEV_ID_82540EM };
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/*
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* May need to specify additional MAC-to-PHY entries --
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* Intel's Windows driver refuses to initialize unless they match
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*/
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enum {
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PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
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E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
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/* default to E1000_DEV_ID_82540EM */ 0xc20
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};
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typedef struct E1000State_st {
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PCIDevice dev;
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NICState *nic;
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NICConf conf;
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MemoryRegion mmio;
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MemoryRegion io;
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uint32_t mac_reg[0x8000];
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uint16_t phy_reg[0x20];
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uint16_t eeprom_data[64];
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uint32_t rxbuf_size;
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uint32_t rxbuf_min_shift;
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int check_rxov;
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struct e1000_tx {
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unsigned char header[256];
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unsigned char vlan_header[4];
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/* Fields vlan and data must not be reordered or separated. */
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unsigned char vlan[4];
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unsigned char data[0x10000];
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uint16_t size;
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unsigned char sum_needed;
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unsigned char vlan_needed;
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uint8_t ipcss;
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uint8_t ipcso;
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uint16_t ipcse;
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uint8_t tucss;
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uint8_t tucso;
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uint16_t tucse;
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uint8_t hdr_len;
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uint16_t mss;
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uint32_t paylen;
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uint16_t tso_frames;
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char tse;
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int8_t ip;
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int8_t tcp;
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char cptse; // current packet tse bit
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} tx;
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struct {
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uint32_t val_in; // shifted in from guest driver
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uint16_t bitnum_in;
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uint16_t bitnum_out;
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uint16_t reading;
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uint32_t old_eecd;
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} eecd_state;
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} E1000State;
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#define defreg(x) x = (E1000_##x>>2)
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enum {
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defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
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defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
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defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
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defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
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defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
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defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
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defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
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defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
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defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
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defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
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defreg(VET),
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};
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enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
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static const char phy_regcap[0x20] = {
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[PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
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[PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
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[PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
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[PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
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[PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
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[PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
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};
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static void
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set_interrupt_cause(E1000State *s, int index, uint32_t val)
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{
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if (val)
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val |= E1000_ICR_INT_ASSERTED;
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s->mac_reg[ICR] = val;
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s->mac_reg[ICS] = val;
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qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
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}
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static void
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set_ics(E1000State *s, int index, uint32_t val)
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{
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DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
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s->mac_reg[IMS]);
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set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
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}
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static int
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rxbufsize(uint32_t v)
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{
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v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
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E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
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E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
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switch (v) {
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case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
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return 16384;
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case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
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return 8192;
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case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
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return 4096;
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case E1000_RCTL_SZ_1024:
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return 1024;
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case E1000_RCTL_SZ_512:
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return 512;
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case E1000_RCTL_SZ_256:
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return 256;
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}
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return 2048;
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}
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static void
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set_ctrl(E1000State *s, int index, uint32_t val)
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{
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/* RST is self clearing */
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s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
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}
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static void
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set_rx_control(E1000State *s, int index, uint32_t val)
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{
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s->mac_reg[RCTL] = val;
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s->rxbuf_size = rxbufsize(val);
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s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
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DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
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s->mac_reg[RCTL]);
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}
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static void
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set_mdic(E1000State *s, int index, uint32_t val)
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{
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uint32_t data = val & E1000_MDIC_DATA_MASK;
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uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
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if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
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val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
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else if (val & E1000_MDIC_OP_READ) {
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DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
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if (!(phy_regcap[addr] & PHY_R)) {
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DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
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val |= E1000_MDIC_ERROR;
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} else
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val = (val ^ data) | s->phy_reg[addr];
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} else if (val & E1000_MDIC_OP_WRITE) {
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DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
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if (!(phy_regcap[addr] & PHY_W)) {
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DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
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val |= E1000_MDIC_ERROR;
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} else
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s->phy_reg[addr] = data;
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}
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s->mac_reg[MDIC] = val | E1000_MDIC_READY;
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set_ics(s, 0, E1000_ICR_MDAC);
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}
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static uint32_t
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get_eecd(E1000State *s, int index)
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{
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uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
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DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
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s->eecd_state.bitnum_out, s->eecd_state.reading);
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if (!s->eecd_state.reading ||
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((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
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((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
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ret |= E1000_EECD_DO;
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return ret;
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}
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static void
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set_eecd(E1000State *s, int index, uint32_t val)
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{
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uint32_t oldval = s->eecd_state.old_eecd;
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s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
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E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
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if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
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return;
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if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
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s->eecd_state.val_in = 0;
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s->eecd_state.bitnum_in = 0;
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s->eecd_state.bitnum_out = 0;
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s->eecd_state.reading = 0;
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}
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if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
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return;
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if (!(E1000_EECD_SK & val)) { // falling edge
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s->eecd_state.bitnum_out++;
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return;
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}
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s->eecd_state.val_in <<= 1;
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if (val & E1000_EECD_DI)
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s->eecd_state.val_in |= 1;
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if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
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s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
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s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
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EEPROM_READ_OPCODE_MICROWIRE);
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}
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DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
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s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
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s->eecd_state.reading);
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}
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static uint32_t
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flash_eerd_read(E1000State *s, int x)
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{
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unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
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if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
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return (s->mac_reg[EERD]);
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if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
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return (E1000_EEPROM_RW_REG_DONE | r);
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return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
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E1000_EEPROM_RW_REG_DONE | r);
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}
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static void
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putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
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{
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uint32_t sum;
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if (cse && cse < n)
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n = cse + 1;
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if (sloc < n-1) {
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sum = net_checksum_add(n-css, data+css);
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cpu_to_be16wu((uint16_t *)(data + sloc),
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net_checksum_finish(sum));
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}
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}
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static inline int
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vlan_enabled(E1000State *s)
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{
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return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
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}
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static inline int
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vlan_rx_filter_enabled(E1000State *s)
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{
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return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
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}
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static inline int
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is_vlan_packet(E1000State *s, const uint8_t *buf)
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{
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return (be16_to_cpup((uint16_t *)(buf + 12)) ==
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le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
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}
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static inline int
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is_vlan_txd(uint32_t txd_lower)
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{
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return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
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}
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/* FCS aka Ethernet CRC-32. We don't get it from backends and can't
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* fill it in, just pad descriptor length by 4 bytes unless guest
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* told us to strip it off the packet. */
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static inline int
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fcs_len(E1000State *s)
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{
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return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
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}
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static void
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xmit_seg(E1000State *s)
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{
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uint16_t len, *sp;
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unsigned int frames = s->tx.tso_frames, css, sofar, n;
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struct e1000_tx *tp = &s->tx;
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if (tp->tse && tp->cptse) {
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css = tp->ipcss;
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DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
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frames, tp->size, css);
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if (tp->ip) { // IPv4
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cpu_to_be16wu((uint16_t *)(tp->data+css+2),
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tp->size - css);
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cpu_to_be16wu((uint16_t *)(tp->data+css+4),
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be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
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} else // IPv6
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cpu_to_be16wu((uint16_t *)(tp->data+css+4),
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tp->size - css);
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css = tp->tucss;
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len = tp->size - css;
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DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
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if (tp->tcp) {
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sofar = frames * tp->mss;
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cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
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be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
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if (tp->paylen - sofar > tp->mss)
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tp->data[css + 13] &= ~9; // PSH, FIN
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} else // UDP
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cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
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if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
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unsigned int phsum;
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// add pseudo-header length before checksum calculation
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sp = (uint16_t *)(tp->data + tp->tucso);
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phsum = be16_to_cpup(sp) + len;
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phsum = (phsum >> 16) + (phsum & 0xffff);
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cpu_to_be16wu(sp, phsum);
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}
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tp->tso_frames++;
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}
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if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
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putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
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if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
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putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
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if (tp->vlan_needed) {
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memmove(tp->vlan, tp->data, 4);
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memmove(tp->data, tp->data + 4, 8);
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memcpy(tp->data + 8, tp->vlan_header, 4);
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qemu_send_packet(&s->nic->nc, tp->vlan, tp->size + 4);
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} else
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qemu_send_packet(&s->nic->nc, tp->data, tp->size);
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s->mac_reg[TPT]++;
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s->mac_reg[GPTC]++;
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n = s->mac_reg[TOTL];
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if ((s->mac_reg[TOTL] += s->tx.size) < n)
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s->mac_reg[TOTH]++;
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}
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static void
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process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
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{
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uint32_t txd_lower = le32_to_cpu(dp->lower.data);
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uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
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unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
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unsigned int msh = 0xfffff, hdr = 0;
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uint64_t addr;
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struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
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struct e1000_tx *tp = &s->tx;
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if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
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op = le32_to_cpu(xp->cmd_and_length);
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tp->ipcss = xp->lower_setup.ip_fields.ipcss;
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tp->ipcso = xp->lower_setup.ip_fields.ipcso;
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tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
|
|
tp->tucss = xp->upper_setup.tcp_fields.tucss;
|
|
tp->tucso = xp->upper_setup.tcp_fields.tucso;
|
|
tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
|
|
tp->paylen = op & 0xfffff;
|
|
tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
|
|
tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
|
|
tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
|
|
tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
|
|
tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
|
|
tp->tso_frames = 0;
|
|
if (tp->tucso == 0) { // this is probably wrong
|
|
DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
|
|
tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
|
|
}
|
|
return;
|
|
} else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
|
|
// data descriptor
|
|
if (tp->size == 0) {
|
|
tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
|
|
}
|
|
tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
|
|
} else {
|
|
// legacy descriptor
|
|
tp->cptse = 0;
|
|
}
|
|
|
|
if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
|
|
(tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
|
|
tp->vlan_needed = 1;
|
|
cpu_to_be16wu((uint16_t *)(tp->vlan_header),
|
|
le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
|
|
cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
|
|
le16_to_cpu(dp->upper.fields.special));
|
|
}
|
|
|
|
addr = le64_to_cpu(dp->buffer_addr);
|
|
if (tp->tse && tp->cptse) {
|
|
hdr = tp->hdr_len;
|
|
msh = hdr + tp->mss;
|
|
do {
|
|
bytes = split_size;
|
|
if (tp->size + bytes > msh)
|
|
bytes = msh - tp->size;
|
|
|
|
bytes = MIN(sizeof(tp->data) - tp->size, bytes);
|
|
pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
|
|
if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
|
|
memmove(tp->header, tp->data, hdr);
|
|
tp->size = sz;
|
|
addr += bytes;
|
|
if (sz == msh) {
|
|
xmit_seg(s);
|
|
memmove(tp->data, tp->header, hdr);
|
|
tp->size = hdr;
|
|
}
|
|
} while (split_size -= bytes);
|
|
} else if (!tp->tse && tp->cptse) {
|
|
// context descriptor TSE is not set, while data descriptor TSE is set
|
|
DBGOUT(TXERR, "TCP segmentaion Error\n");
|
|
} else {
|
|
split_size = MIN(sizeof(tp->data) - tp->size, split_size);
|
|
pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
|
|
tp->size += split_size;
|
|
}
|
|
|
|
if (!(txd_lower & E1000_TXD_CMD_EOP))
|
|
return;
|
|
if (!(tp->tse && tp->cptse && tp->size < hdr))
|
|
xmit_seg(s);
|
|
tp->tso_frames = 0;
|
|
tp->sum_needed = 0;
|
|
tp->vlan_needed = 0;
|
|
tp->size = 0;
|
|
tp->cptse = 0;
|
|
}
|
|
|
|
static uint32_t
|
|
txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
|
|
{
|
|
uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
|
|
|
|
if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
|
|
return 0;
|
|
txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
|
|
~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
|
|
dp->upper.data = cpu_to_le32(txd_upper);
|
|
pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
|
|
&dp->upper, sizeof(dp->upper));
|
|
return E1000_ICR_TXDW;
|
|
}
|
|
|
|
static uint64_t tx_desc_base(E1000State *s)
|
|
{
|
|
uint64_t bah = s->mac_reg[TDBAH];
|
|
uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
|
|
|
|
return (bah << 32) + bal;
|
|
}
|
|
|
|
static void
|
|
start_xmit(E1000State *s)
|
|
{
|
|
dma_addr_t base;
|
|
struct e1000_tx_desc desc;
|
|
uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
|
|
|
|
if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
|
|
DBGOUT(TX, "tx disabled\n");
|
|
return;
|
|
}
|
|
|
|
while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
|
|
base = tx_desc_base(s) +
|
|
sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
|
|
pci_dma_read(&s->dev, base, &desc, sizeof(desc));
|
|
|
|
DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
|
|
(void *)(intptr_t)desc.buffer_addr, desc.lower.data,
|
|
desc.upper.data);
|
|
|
|
process_tx_desc(s, &desc);
|
|
cause |= txdesc_writeback(s, base, &desc);
|
|
|
|
if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
|
|
s->mac_reg[TDH] = 0;
|
|
/*
|
|
* the following could happen only if guest sw assigns
|
|
* bogus values to TDT/TDLEN.
|
|
* there's nothing too intelligent we could do about this.
|
|
*/
|
|
if (s->mac_reg[TDH] == tdh_start) {
|
|
DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
|
|
tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
|
|
break;
|
|
}
|
|
}
|
|
set_ics(s, 0, cause);
|
|
}
|
|
|
|
static int
|
|
receive_filter(E1000State *s, const uint8_t *buf, int size)
|
|
{
|
|
static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
|
|
static const int mta_shift[] = {4, 3, 2, 0};
|
|
uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
|
|
|
|
if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
|
|
uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
|
|
uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
|
|
((vid >> 5) & 0x7f));
|
|
if ((vfta & (1 << (vid & 0x1f))) == 0)
|
|
return 0;
|
|
}
|
|
|
|
if (rctl & E1000_RCTL_UPE) // promiscuous
|
|
return 1;
|
|
|
|
if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
|
|
return 1;
|
|
|
|
if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
|
|
return 1;
|
|
|
|
for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
|
|
if (!(rp[1] & E1000_RAH_AV))
|
|
continue;
|
|
ra[0] = cpu_to_le32(rp[0]);
|
|
ra[1] = cpu_to_le32(rp[1]);
|
|
if (!memcmp(buf, (uint8_t *)ra, 6)) {
|
|
DBGOUT(RXFILTER,
|
|
"unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
|
(int)(rp - s->mac_reg - RA)/2,
|
|
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
|
|
return 1;
|
|
}
|
|
}
|
|
DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
|
|
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
|
|
|
|
f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
|
|
f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
|
|
if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
|
|
return 1;
|
|
DBGOUT(RXFILTER,
|
|
"dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
|
|
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
|
|
(rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
|
|
s->mac_reg[MTA + (f >> 5)]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
e1000_set_link_status(VLANClientState *nc)
|
|
{
|
|
E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
|
uint32_t old_status = s->mac_reg[STATUS];
|
|
|
|
if (nc->link_down) {
|
|
s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
|
|
s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
|
|
} else {
|
|
s->mac_reg[STATUS] |= E1000_STATUS_LU;
|
|
s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
|
|
}
|
|
|
|
if (s->mac_reg[STATUS] != old_status)
|
|
set_ics(s, 0, E1000_ICR_LSC);
|
|
}
|
|
|
|
static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
|
|
{
|
|
int bufs;
|
|
/* Fast-path short packets */
|
|
if (total_size <= s->rxbuf_size) {
|
|
return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov;
|
|
}
|
|
if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
|
|
bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
|
|
} else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) {
|
|
bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
|
|
s->mac_reg[RDT] - s->mac_reg[RDH];
|
|
} else {
|
|
return false;
|
|
}
|
|
return total_size <= bufs * s->rxbuf_size;
|
|
}
|
|
|
|
static int
|
|
e1000_can_receive(VLANClientState *nc)
|
|
{
|
|
E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
|
|
|
return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
|
|
}
|
|
|
|
static uint64_t rx_desc_base(E1000State *s)
|
|
{
|
|
uint64_t bah = s->mac_reg[RDBAH];
|
|
uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
|
|
|
|
return (bah << 32) + bal;
|
|
}
|
|
|
|
static ssize_t
|
|
e1000_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
|
|
{
|
|
E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
|
struct e1000_rx_desc desc;
|
|
dma_addr_t base;
|
|
unsigned int n, rdt;
|
|
uint32_t rdh_start;
|
|
uint16_t vlan_special = 0;
|
|
uint8_t vlan_status = 0, vlan_offset = 0;
|
|
uint8_t min_buf[MIN_BUF_SIZE];
|
|
size_t desc_offset;
|
|
size_t desc_size;
|
|
size_t total_size;
|
|
|
|
if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
|
|
return -1;
|
|
|
|
/* Pad to minimum Ethernet frame length */
|
|
if (size < sizeof(min_buf)) {
|
|
memcpy(min_buf, buf, size);
|
|
memset(&min_buf[size], 0, sizeof(min_buf) - size);
|
|
buf = min_buf;
|
|
size = sizeof(min_buf);
|
|
}
|
|
|
|
if (!receive_filter(s, buf, size))
|
|
return size;
|
|
|
|
if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
|
|
vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
|
|
memmove((uint8_t *)buf + 4, buf, 12);
|
|
vlan_status = E1000_RXD_STAT_VP;
|
|
vlan_offset = 4;
|
|
size -= 4;
|
|
}
|
|
|
|
rdh_start = s->mac_reg[RDH];
|
|
desc_offset = 0;
|
|
total_size = size + fcs_len(s);
|
|
if (!e1000_has_rxbufs(s, total_size)) {
|
|
set_ics(s, 0, E1000_ICS_RXO);
|
|
return -1;
|
|
}
|
|
do {
|
|
desc_size = total_size - desc_offset;
|
|
if (desc_size > s->rxbuf_size) {
|
|
desc_size = s->rxbuf_size;
|
|
}
|
|
base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
|
|
pci_dma_read(&s->dev, base, &desc, sizeof(desc));
|
|
desc.special = vlan_special;
|
|
desc.status |= (vlan_status | E1000_RXD_STAT_DD);
|
|
if (desc.buffer_addr) {
|
|
if (desc_offset < size) {
|
|
size_t copy_size = size - desc_offset;
|
|
if (copy_size > s->rxbuf_size) {
|
|
copy_size = s->rxbuf_size;
|
|
}
|
|
pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
|
|
buf + desc_offset + vlan_offset, copy_size);
|
|
}
|
|
desc_offset += desc_size;
|
|
desc.length = cpu_to_le16(desc_size);
|
|
if (desc_offset >= total_size) {
|
|
desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
|
|
} else {
|
|
/* Guest zeroing out status is not a hardware requirement.
|
|
Clear EOP in case guest didn't do it. */
|
|
desc.status &= ~E1000_RXD_STAT_EOP;
|
|
}
|
|
} else { // as per intel docs; skip descriptors with null buf addr
|
|
DBGOUT(RX, "Null RX descriptor!!\n");
|
|
}
|
|
pci_dma_write(&s->dev, base, &desc, sizeof(desc));
|
|
|
|
if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
|
|
s->mac_reg[RDH] = 0;
|
|
s->check_rxov = 1;
|
|
/* see comment in start_xmit; same here */
|
|
if (s->mac_reg[RDH] == rdh_start) {
|
|
DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
|
|
rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
|
|
set_ics(s, 0, E1000_ICS_RXO);
|
|
return -1;
|
|
}
|
|
} while (desc_offset < total_size);
|
|
|
|
s->mac_reg[GPRC]++;
|
|
s->mac_reg[TPR]++;
|
|
/* TOR - Total Octets Received:
|
|
* This register includes bytes received in a packet from the <Destination
|
|
* Address> field through the <CRC> field, inclusively.
|
|
*/
|
|
n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
|
|
if (n < s->mac_reg[TORL])
|
|
s->mac_reg[TORH]++;
|
|
s->mac_reg[TORL] = n;
|
|
|
|
n = E1000_ICS_RXT0;
|
|
if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
|
|
rdt += s->mac_reg[RDLEN] / sizeof(desc);
|
|
if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
|
|
s->rxbuf_min_shift)
|
|
n |= E1000_ICS_RXDMT0;
|
|
|
|
set_ics(s, 0, n);
|
|
|
|
return size;
|
|
}
|
|
|
|
static uint32_t
|
|
mac_readreg(E1000State *s, int index)
|
|
{
|
|
return s->mac_reg[index];
|
|
}
|
|
|
|
static uint32_t
|
|
mac_icr_read(E1000State *s, int index)
|
|
{
|
|
uint32_t ret = s->mac_reg[ICR];
|
|
|
|
DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
|
|
set_interrupt_cause(s, 0, 0);
|
|
return ret;
|
|
}
|
|
|
|
static uint32_t
|
|
mac_read_clr4(E1000State *s, int index)
|
|
{
|
|
uint32_t ret = s->mac_reg[index];
|
|
|
|
s->mac_reg[index] = 0;
|
|
return ret;
|
|
}
|
|
|
|
static uint32_t
|
|
mac_read_clr8(E1000State *s, int index)
|
|
{
|
|
uint32_t ret = s->mac_reg[index];
|
|
|
|
s->mac_reg[index] = 0;
|
|
s->mac_reg[index-1] = 0;
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
mac_writereg(E1000State *s, int index, uint32_t val)
|
|
{
|
|
s->mac_reg[index] = val;
|
|
}
|
|
|
|
static void
|
|
set_rdt(E1000State *s, int index, uint32_t val)
|
|
{
|
|
s->check_rxov = 0;
|
|
s->mac_reg[index] = val & 0xffff;
|
|
}
|
|
|
|
static void
|
|
set_16bit(E1000State *s, int index, uint32_t val)
|
|
{
|
|
s->mac_reg[index] = val & 0xffff;
|
|
}
|
|
|
|
static void
|
|
set_dlen(E1000State *s, int index, uint32_t val)
|
|
{
|
|
s->mac_reg[index] = val & 0xfff80;
|
|
}
|
|
|
|
static void
|
|
set_tctl(E1000State *s, int index, uint32_t val)
|
|
{
|
|
s->mac_reg[index] = val;
|
|
s->mac_reg[TDT] &= 0xffff;
|
|
start_xmit(s);
|
|
}
|
|
|
|
static void
|
|
set_icr(E1000State *s, int index, uint32_t val)
|
|
{
|
|
DBGOUT(INTERRUPT, "set_icr %x\n", val);
|
|
set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
|
|
}
|
|
|
|
static void
|
|
set_imc(E1000State *s, int index, uint32_t val)
|
|
{
|
|
s->mac_reg[IMS] &= ~val;
|
|
set_ics(s, 0, 0);
|
|
}
|
|
|
|
static void
|
|
set_ims(E1000State *s, int index, uint32_t val)
|
|
{
|
|
s->mac_reg[IMS] |= val;
|
|
set_ics(s, 0, 0);
|
|
}
|
|
|
|
#define getreg(x) [x] = mac_readreg
|
|
static uint32_t (*macreg_readops[])(E1000State *, int) = {
|
|
getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
|
|
getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
|
|
getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
|
|
getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
|
|
getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
|
|
getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
|
|
getreg(TDLEN), getreg(RDLEN),
|
|
|
|
[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
|
|
[GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
|
|
[ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
|
|
[CRCERRS ... MPC] = &mac_readreg,
|
|
[RA ... RA+31] = &mac_readreg,
|
|
[MTA ... MTA+127] = &mac_readreg,
|
|
[VFTA ... VFTA+127] = &mac_readreg,
|
|
};
|
|
enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
|
|
|
|
#define putreg(x) [x] = mac_writereg
|
|
static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
|
|
putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
|
|
putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
|
|
putreg(RDBAL), putreg(LEDCTL), putreg(VET),
|
|
[TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
|
|
[TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
|
|
[TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
|
|
[IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
|
|
[EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
|
|
[RA ... RA+31] = &mac_writereg,
|
|
[MTA ... MTA+127] = &mac_writereg,
|
|
[VFTA ... VFTA+127] = &mac_writereg,
|
|
};
|
|
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
|
|
|
|
static void
|
|
e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
|
|
unsigned size)
|
|
{
|
|
E1000State *s = opaque;
|
|
unsigned int index = (addr & 0x1ffff) >> 2;
|
|
|
|
if (index < NWRITEOPS && macreg_writeops[index]) {
|
|
macreg_writeops[index](s, index, val);
|
|
} else if (index < NREADOPS && macreg_readops[index]) {
|
|
DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
|
|
} else {
|
|
DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
|
|
index<<2, val);
|
|
}
|
|
}
|
|
|
|
static uint64_t
|
|
e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
|
|
{
|
|
E1000State *s = opaque;
|
|
unsigned int index = (addr & 0x1ffff) >> 2;
|
|
|
|
if (index < NREADOPS && macreg_readops[index])
|
|
{
|
|
return macreg_readops[index](s, index);
|
|
}
|
|
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
|
|
return 0;
|
|
}
|
|
|
|
static const MemoryRegionOps e1000_mmio_ops = {
|
|
.read = e1000_mmio_read,
|
|
.write = e1000_mmio_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.impl = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
},
|
|
};
|
|
|
|
static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
|
|
unsigned size)
|
|
{
|
|
E1000State *s = opaque;
|
|
|
|
(void)s;
|
|
return 0;
|
|
}
|
|
|
|
static void e1000_io_write(void *opaque, target_phys_addr_t addr,
|
|
uint64_t val, unsigned size)
|
|
{
|
|
E1000State *s = opaque;
|
|
|
|
(void)s;
|
|
}
|
|
|
|
static const MemoryRegionOps e1000_io_ops = {
|
|
.read = e1000_io_read,
|
|
.write = e1000_io_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
static bool is_version_1(void *opaque, int version_id)
|
|
{
|
|
return version_id == 1;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_e1000 = {
|
|
.name = "e1000",
|
|
.version_id = 2,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_PCI_DEVICE(dev, E1000State),
|
|
VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
|
|
VMSTATE_UNUSED(4), /* Was mmio_base. */
|
|
VMSTATE_UINT32(rxbuf_size, E1000State),
|
|
VMSTATE_UINT32(rxbuf_min_shift, E1000State),
|
|
VMSTATE_UINT32(eecd_state.val_in, E1000State),
|
|
VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
|
|
VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
|
|
VMSTATE_UINT16(eecd_state.reading, E1000State),
|
|
VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
|
|
VMSTATE_UINT8(tx.ipcss, E1000State),
|
|
VMSTATE_UINT8(tx.ipcso, E1000State),
|
|
VMSTATE_UINT16(tx.ipcse, E1000State),
|
|
VMSTATE_UINT8(tx.tucss, E1000State),
|
|
VMSTATE_UINT8(tx.tucso, E1000State),
|
|
VMSTATE_UINT16(tx.tucse, E1000State),
|
|
VMSTATE_UINT32(tx.paylen, E1000State),
|
|
VMSTATE_UINT8(tx.hdr_len, E1000State),
|
|
VMSTATE_UINT16(tx.mss, E1000State),
|
|
VMSTATE_UINT16(tx.size, E1000State),
|
|
VMSTATE_UINT16(tx.tso_frames, E1000State),
|
|
VMSTATE_UINT8(tx.sum_needed, E1000State),
|
|
VMSTATE_INT8(tx.ip, E1000State),
|
|
VMSTATE_INT8(tx.tcp, E1000State),
|
|
VMSTATE_BUFFER(tx.header, E1000State),
|
|
VMSTATE_BUFFER(tx.data, E1000State),
|
|
VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
|
|
VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
|
|
VMSTATE_UINT32(mac_reg[CTRL], E1000State),
|
|
VMSTATE_UINT32(mac_reg[EECD], E1000State),
|
|
VMSTATE_UINT32(mac_reg[EERD], E1000State),
|
|
VMSTATE_UINT32(mac_reg[GPRC], E1000State),
|
|
VMSTATE_UINT32(mac_reg[GPTC], E1000State),
|
|
VMSTATE_UINT32(mac_reg[ICR], E1000State),
|
|
VMSTATE_UINT32(mac_reg[ICS], E1000State),
|
|
VMSTATE_UINT32(mac_reg[IMC], E1000State),
|
|
VMSTATE_UINT32(mac_reg[IMS], E1000State),
|
|
VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
|
|
VMSTATE_UINT32(mac_reg[MANC], E1000State),
|
|
VMSTATE_UINT32(mac_reg[MDIC], E1000State),
|
|
VMSTATE_UINT32(mac_reg[MPC], E1000State),
|
|
VMSTATE_UINT32(mac_reg[PBA], E1000State),
|
|
VMSTATE_UINT32(mac_reg[RCTL], E1000State),
|
|
VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
|
|
VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
|
|
VMSTATE_UINT32(mac_reg[RDH], E1000State),
|
|
VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
|
|
VMSTATE_UINT32(mac_reg[RDT], E1000State),
|
|
VMSTATE_UINT32(mac_reg[STATUS], E1000State),
|
|
VMSTATE_UINT32(mac_reg[SWSM], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TCTL], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TDH], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TDT], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TORH], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TORL], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TOTH], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TOTL], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TPR], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TPT], E1000State),
|
|
VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
|
|
VMSTATE_UINT32(mac_reg[WUFC], E1000State),
|
|
VMSTATE_UINT32(mac_reg[VET], E1000State),
|
|
VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
|
|
VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
|
|
VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const uint16_t e1000_eeprom_template[64] = {
|
|
0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
|
|
0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
|
|
0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
|
|
0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
|
|
0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
|
|
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
|
|
0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
|
|
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
|
|
};
|
|
|
|
static const uint16_t phy_reg_init[] = {
|
|
[PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
|
|
[PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
|
|
[PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
|
|
[M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
|
|
[PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
|
|
[M88E1000_PHY_SPEC_STATUS] = 0xac00,
|
|
};
|
|
|
|
static const uint32_t mac_reg_init[] = {
|
|
[PBA] = 0x00100030,
|
|
[LEDCTL] = 0x602,
|
|
[CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
|
|
E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
|
|
[STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
|
|
E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
|
|
E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
|
|
E1000_STATUS_LU,
|
|
[MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
|
|
E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
|
|
E1000_MANC_RMCP_EN,
|
|
};
|
|
|
|
/* PCI interface */
|
|
|
|
static void
|
|
e1000_mmio_setup(E1000State *d)
|
|
{
|
|
int i;
|
|
const uint32_t excluded_regs[] = {
|
|
E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
|
|
E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
|
|
};
|
|
|
|
memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
|
|
PNPMMIO_SIZE);
|
|
memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
|
|
for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
|
|
memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
|
|
excluded_regs[i+1] - excluded_regs[i] - 4);
|
|
memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
|
|
}
|
|
|
|
static void
|
|
e1000_cleanup(VLANClientState *nc)
|
|
{
|
|
E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
|
|
|
s->nic = NULL;
|
|
}
|
|
|
|
static int
|
|
pci_e1000_uninit(PCIDevice *dev)
|
|
{
|
|
E1000State *d = DO_UPCAST(E1000State, dev, dev);
|
|
|
|
memory_region_destroy(&d->mmio);
|
|
memory_region_destroy(&d->io);
|
|
qemu_del_vlan_client(&d->nic->nc);
|
|
return 0;
|
|
}
|
|
|
|
static void e1000_reset(void *opaque)
|
|
{
|
|
E1000State *d = opaque;
|
|
|
|
memset(d->phy_reg, 0, sizeof d->phy_reg);
|
|
memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
|
|
memset(d->mac_reg, 0, sizeof d->mac_reg);
|
|
memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
|
|
d->rxbuf_min_shift = 1;
|
|
memset(&d->tx, 0, sizeof d->tx);
|
|
|
|
if (d->nic->nc.link_down) {
|
|
d->mac_reg[STATUS] &= ~E1000_STATUS_LU;
|
|
d->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
|
|
}
|
|
}
|
|
|
|
static NetClientInfo net_e1000_info = {
|
|
.type = NET_CLIENT_TYPE_NIC,
|
|
.size = sizeof(NICState),
|
|
.can_receive = e1000_can_receive,
|
|
.receive = e1000_receive,
|
|
.cleanup = e1000_cleanup,
|
|
.link_status_changed = e1000_set_link_status,
|
|
};
|
|
|
|
static int pci_e1000_init(PCIDevice *pci_dev)
|
|
{
|
|
E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
|
|
uint8_t *pci_conf;
|
|
uint16_t checksum = 0;
|
|
int i;
|
|
uint8_t *macaddr;
|
|
|
|
pci_conf = d->dev.config;
|
|
|
|
/* TODO: RST# value should be 0, PCI spec 6.2.4 */
|
|
pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
|
|
|
|
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
|
|
|
|
e1000_mmio_setup(d);
|
|
|
|
pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
|
|
|
|
pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
|
|
|
|
memmove(d->eeprom_data, e1000_eeprom_template,
|
|
sizeof e1000_eeprom_template);
|
|
qemu_macaddr_default_if_unset(&d->conf.macaddr);
|
|
macaddr = d->conf.macaddr.a;
|
|
for (i = 0; i < 3; i++)
|
|
d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
|
|
for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
|
|
checksum += d->eeprom_data[i];
|
|
checksum = (uint16_t) EEPROM_SUM - checksum;
|
|
d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
|
|
|
|
d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
|
|
object_get_typename(OBJECT(d)), d->dev.qdev.id, d);
|
|
|
|
qemu_format_nic_info_str(&d->nic->nc, macaddr);
|
|
|
|
add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void qdev_e1000_reset(DeviceState *dev)
|
|
{
|
|
E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
|
|
e1000_reset(d);
|
|
}
|
|
|
|
static Property e1000_properties[] = {
|
|
DEFINE_NIC_PROPERTIES(E1000State, conf),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void e1000_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->init = pci_e1000_init;
|
|
k->exit = pci_e1000_uninit;
|
|
k->romfile = "pxe-e1000.rom";
|
|
k->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
k->device_id = E1000_DEVID;
|
|
k->revision = 0x03;
|
|
k->class_id = PCI_CLASS_NETWORK_ETHERNET;
|
|
}
|
|
|
|
static DeviceInfo e1000_info = {
|
|
.name = "e1000",
|
|
.desc = "Intel Gigabit Ethernet",
|
|
.size = sizeof(E1000State),
|
|
.reset = qdev_e1000_reset,
|
|
.vmsd = &vmstate_e1000,
|
|
.props = e1000_properties,
|
|
.class_init = e1000_class_init,
|
|
};
|
|
|
|
static void e1000_register_devices(void)
|
|
{
|
|
pci_qdev_register(&e1000_info);
|
|
}
|
|
|
|
device_init(e1000_register_devices)
|