qemu-e2k/gdb-xml
Jonathan Behrens ab9056ff9b
target/riscv: Expose "priv" register for GDB for reads
This patch enables a debugger to read the current privilege level via a virtual
"priv" register. When compiled with CONFIG_USER_ONLY the register is still
visible but always reports the value zero.

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-10-28 07:47:29 -07:00
..
aarch64-core.xml
aarch64-fpu.xml
arm-core.xml
arm-neon.xml
arm-vfp3.xml
arm-vfp.xml
cf-core.xml
cf-fp.xml
i386-32bit.xml
i386-64bit.xml
m68k-fp.xml
power64-core.xml
power-altivec.xml
power-core.xml
power-fpu.xml
power-spe.xml
power-vsx.xml
riscv-32bit-cpu.xml RISC-V: Add 32-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-32bit-csr.xml RISC-V: Add 32-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-32bit-fpu.xml RISC-V: Add 64-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-32bit-virtual.xml target/riscv: Expose "priv" register for GDB for reads 2019-10-28 07:47:29 -07:00
riscv-64bit-cpu.xml RISC-V: Add 64-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-64bit-csr.xml RISC-V: Add 64-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-64bit-fpu.xml RISC-V: Add 64-bit gdb xml files. 2019-03-19 05:13:24 -07:00
riscv-64bit-virtual.xml target/riscv: Expose "priv" register for GDB for reads 2019-10-28 07:47:29 -07:00
s390-acr.xml
s390-cr.xml
s390-fpr.xml
s390-gs.xml
s390-virt.xml
s390-vx.xml
s390x-core64.xml