5fafdf24ef
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
191 lines
3.8 KiB
C
191 lines
3.8 KiB
C
/*
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* i386 micro operations (templates for various register related
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* operations)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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void OPPROTO glue(op_movl_A0,REGNAME)(void)
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{
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A0 = (uint32_t)REG;
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}
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void OPPROTO glue(op_addl_A0,REGNAME)(void)
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{
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A0 = (uint32_t)(A0 + REG);
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}
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void OPPROTO glue(glue(op_addl_A0,REGNAME),_s1)(void)
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{
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A0 = (uint32_t)(A0 + (REG << 1));
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}
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void OPPROTO glue(glue(op_addl_A0,REGNAME),_s2)(void)
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{
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A0 = (uint32_t)(A0 + (REG << 2));
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}
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void OPPROTO glue(glue(op_addl_A0,REGNAME),_s3)(void)
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{
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A0 = (uint32_t)(A0 + (REG << 3));
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}
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#ifdef TARGET_X86_64
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void OPPROTO glue(op_movq_A0,REGNAME)(void)
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{
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A0 = REG;
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}
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void OPPROTO glue(op_addq_A0,REGNAME)(void)
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{
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A0 = (A0 + REG);
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}
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void OPPROTO glue(glue(op_addq_A0,REGNAME),_s1)(void)
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{
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A0 = (A0 + (REG << 1));
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}
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void OPPROTO glue(glue(op_addq_A0,REGNAME),_s2)(void)
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{
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A0 = (A0 + (REG << 2));
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}
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void OPPROTO glue(glue(op_addq_A0,REGNAME),_s3)(void)
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{
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A0 = (A0 + (REG << 3));
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}
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#endif
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void OPPROTO glue(op_movl_T0,REGNAME)(void)
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{
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T0 = REG;
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}
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void OPPROTO glue(op_movl_T1,REGNAME)(void)
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{
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T1 = REG;
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}
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void OPPROTO glue(op_movh_T0,REGNAME)(void)
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{
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T0 = REG >> 8;
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}
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void OPPROTO glue(op_movh_T1,REGNAME)(void)
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{
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T1 = REG >> 8;
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}
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void OPPROTO glue(glue(op_movl,REGNAME),_T0)(void)
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{
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REG = (uint32_t)T0;
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}
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void OPPROTO glue(glue(op_movl,REGNAME),_T1)(void)
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{
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REG = (uint32_t)T1;
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}
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void OPPROTO glue(glue(op_movl,REGNAME),_A0)(void)
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{
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REG = (uint32_t)A0;
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}
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#ifdef TARGET_X86_64
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void OPPROTO glue(glue(op_movq,REGNAME),_T0)(void)
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{
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REG = T0;
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}
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void OPPROTO glue(glue(op_movq,REGNAME),_T1)(void)
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{
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REG = T1;
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}
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void OPPROTO glue(glue(op_movq,REGNAME),_A0)(void)
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{
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REG = A0;
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}
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#endif
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/* mov T1 to REG if T0 is true */
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void OPPROTO glue(glue(op_cmovw,REGNAME),_T1_T0)(void)
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{
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if (T0)
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REG = (REG & ~0xffff) | (T1 & 0xffff);
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FORCE_RET();
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}
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void OPPROTO glue(glue(op_cmovl,REGNAME),_T1_T0)(void)
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{
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if (T0)
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REG = (uint32_t)T1;
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FORCE_RET();
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}
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#ifdef TARGET_X86_64
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void OPPROTO glue(glue(op_cmovq,REGNAME),_T1_T0)(void)
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{
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if (T0)
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REG = T1;
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FORCE_RET();
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}
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#endif
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/* NOTE: T0 high order bits are ignored */
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void OPPROTO glue(glue(op_movw,REGNAME),_T0)(void)
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{
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REG = (REG & ~0xffff) | (T0 & 0xffff);
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}
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/* NOTE: T0 high order bits are ignored */
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void OPPROTO glue(glue(op_movw,REGNAME),_T1)(void)
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{
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REG = (REG & ~0xffff) | (T1 & 0xffff);
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}
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/* NOTE: A0 high order bits are ignored */
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void OPPROTO glue(glue(op_movw,REGNAME),_A0)(void)
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{
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REG = (REG & ~0xffff) | (A0 & 0xffff);
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}
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/* NOTE: T0 high order bits are ignored */
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void OPPROTO glue(glue(op_movb,REGNAME),_T0)(void)
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{
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REG = (REG & ~0xff) | (T0 & 0xff);
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}
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/* NOTE: T0 high order bits are ignored */
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void OPPROTO glue(glue(op_movh,REGNAME),_T0)(void)
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{
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REG = (REG & ~0xff00) | ((T0 & 0xff) << 8);
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}
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/* NOTE: T1 high order bits are ignored */
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void OPPROTO glue(glue(op_movb,REGNAME),_T1)(void)
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{
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REG = (REG & ~0xff) | (T1 & 0xff);
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}
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/* NOTE: T1 high order bits are ignored */
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void OPPROTO glue(glue(op_movh,REGNAME),_T1)(void)
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{
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REG = (REG & ~0xff00) | ((T1 & 0xff) << 8);
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}
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