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qemu-e2k/target-xtensa
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Max Filippov ab58c5b4fd target-xtensa: add DEBUGCAUSE SR and configuration 
DEBUGCAUSE SR holds information about the most recent debug exception.
See ISA, 4.7.7 for more details.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
 		2012-02-18 14:55:51 +04:00
..
core-dc232b target-xtensa: add dc232b core 2011-10-16 10:40:02 +00:00
core-fsf target-xtensa: add fsf core 2011-10-16 10:40:16 +00:00
core-dc232b.c target-xtensa: add dc232b core 2011-10-16 10:40:02 +00:00
core-fsf.c target-xtensa: add fsf core 2011-10-16 10:40:16 +00:00
cpu.h target-xtensa: add DEBUGCAUSE SR and configuration 2012-02-18 14:55:51 +04:00
helper.c target-xtensa: implement info tlb monitor command 2012-02-18 01:25:28 +04:00
helpers.h target-xtensa: implement memory protection options 2011-09-10 16:57:40 +00:00
machine.c target-xtensa: add target stubs 2011-09-10 16:57:36 +00:00
op_helper.c target-xtensa: fix guest hang on masked CCOMPARE interrupt 2011-10-15 21:03:03 +00:00
overlay_tool.h target-xtensa: define TLB_TEMPLATE for MMU-less cores 2012-02-18 01:25:27 +04:00
translate.c target-xtensa: add DEBUGCAUSE SR and configuration 2012-02-18 14:55:51 +04:00