OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity
abd9a20665
qemu-e2k/target/riscv/insn_trans
History
Dao Lu 4696f0ab5c target/riscv: Add Zihintpause support 
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.

Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Dao Lu <daolu@rivosinc.com>
Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07 09:18:33 +02:00
..
trans_privileged.c.inc target/riscv: Minimize the calls to decode_save_opc 2022-07-03 10:03:20 +10:00
trans_rva.c.inc target/riscv: Calculate address according to XLEN 2022-01-21 15:52:57 +10:00
trans_rvb.c.inc target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
trans_rvd.c.inc target/riscv: add support for zdinx 2022-03-03 13:14:50 +10:00
trans_rvf.c.inc target/riscv: add support for zfinx 2022-03-03 13:14:50 +10:00
trans_rvh.c.inc target/riscv: Minimize the calls to decode_save_opc 2022-07-03 10:03:20 +10:00
trans_rvi.c.inc target/riscv: Add Zihintpause support 2022-09-07 09:18:33 +02:00
trans_rvk.c.inc target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
trans_rvm.c.inc target/riscv: add support for zmmul extension v0.1 2022-06-10 09:31:42 +10:00
trans_rvv.c.inc target/riscv: rvv: Add mask agnostic for vector permutation instructions 2022-09-07 09:18:33 +02:00
trans_rvzfh.c.inc target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
trans_svinval.c.inc target/riscv: add support for svinval extension 2022-02-16 12:25:52 +10:00
trans_xventanacondops.c.inc target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00