392 lines
12 KiB
C
392 lines
12 KiB
C
/*
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* s390 PCI BUS definitions
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*
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* Copyright 2014 IBM Corp.
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* Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
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* Hong Bo Li <lihbbj@cn.ibm.com>
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* Yi Min Zhao <zyimin@cn.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at
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* your option) any later version. See the COPYING file in the top-level
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* directory.
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*/
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#ifndef HW_S390_PCI_BUS_H
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#define HW_S390_PCI_BUS_H
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/s390x/sclp.h"
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#include "hw/s390x/s390_flic.h"
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#include "hw/s390x/css.h"
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#include "hw/s390x/s390-pci-clp.h"
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#include "qom/object.h"
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#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
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#define TYPE_S390_PCI_BUS "s390-pcibus"
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#define TYPE_S390_PCI_DEVICE "zpci"
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#define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
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#define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region"
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#define FH_MASK_ENABLE 0x80000000
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#define FH_MASK_INSTANCE 0x7f000000
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#define FH_MASK_SHM 0x00ff0000
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#define FH_MASK_INDEX 0x0000ffff
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#define FH_SHM_VFIO 0x00010000
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#define FH_SHM_EMUL 0x00020000
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#define ZPCI_MAX_FID 0xffffffff
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#define ZPCI_MAX_UID 0xffff
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#define UID_UNDEFINED 0
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#define UID_CHECKING_ENABLED 0x01
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OBJECT_DECLARE_SIMPLE_TYPE(S390pciState, S390_PCI_HOST_BRIDGE)
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OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBus, S390_PCI_BUS)
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OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBusDevice, S390_PCI_DEVICE)
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OBJECT_DECLARE_SIMPLE_TYPE(S390PCIIOMMU, S390_PCI_IOMMU)
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#define HP_EVENT_TO_CONFIGURED 0x0301
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#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
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#define HP_EVENT_DECONFIGURE_REQUEST 0x0303
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#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
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#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
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#define ERR_EVENT_INVALAS 0x1
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#define ERR_EVENT_OORANGE 0x2
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#define ERR_EVENT_INVALTF 0x3
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#define ERR_EVENT_TPROTE 0x4
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#define ERR_EVENT_APROTE 0x5
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#define ERR_EVENT_KEYE 0x6
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#define ERR_EVENT_INVALTE 0x7
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#define ERR_EVENT_INVALTL 0x8
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#define ERR_EVENT_TT 0x9
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#define ERR_EVENT_INVALMS 0xa
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#define ERR_EVENT_SERR 0xb
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#define ERR_EVENT_NOMSI 0x10
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#define ERR_EVENT_INVALBV 0x11
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#define ERR_EVENT_AIBV 0x12
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#define ERR_EVENT_AIRERR 0x13
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#define ERR_EVENT_FMBA 0x2a
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#define ERR_EVENT_FMBUP 0x2b
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#define ERR_EVENT_FMBPRO 0x2c
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#define ERR_EVENT_CCONF 0x30
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#define ERR_EVENT_SERVAC 0x3a
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#define ERR_EVENT_PERMERR 0x3b
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#define ERR_EVENT_Q_BIT 0x2
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#define ERR_EVENT_MVN_OFFSET 16
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#define ZPCI_MSI_VEC_BITS 11
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#define ZPCI_MSI_VEC_MASK 0x7ff
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#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
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#define ZPCI_SDMA_ADDR 0x100000000ULL
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#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
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#define PAGE_DEFAULT_ACC 0
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#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
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/* I/O Translation Anchor (IOTA) */
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enum ZpciIoatDtype {
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ZPCI_IOTA_STO = 0,
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ZPCI_IOTA_RTTO = 1,
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ZPCI_IOTA_RSTO = 2,
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ZPCI_IOTA_RFTO = 3,
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ZPCI_IOTA_PFAA = 4,
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ZPCI_IOTA_IOPFAA = 5,
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ZPCI_IOTA_IOPTO = 7
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};
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#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
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#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
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#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
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#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
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#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
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#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
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#define ZPCI_IOTA_FS_4K 0
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#define ZPCI_IOTA_FS_1M 1
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#define ZPCI_IOTA_FS_2G 2
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#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
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#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
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#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
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#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
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#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
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#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
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ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
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/* I/O Region and segment tables */
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#define ZPCI_INDEX_MASK 0x7ffULL
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#define ZPCI_TABLE_TYPE_MASK 0xc
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#define ZPCI_TABLE_TYPE_RFX 0xc
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#define ZPCI_TABLE_TYPE_RSX 0x8
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#define ZPCI_TABLE_TYPE_RTX 0x4
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#define ZPCI_TABLE_TYPE_SX 0x0
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#define ZPCI_TABLE_LEN_RFX 0x3
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#define ZPCI_TABLE_LEN_RSX 0x3
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#define ZPCI_TABLE_LEN_RTX 0x3
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#define ZPCI_TABLE_OFFSET_MASK 0xc0
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#define ZPCI_TABLE_SIZE 0x4000
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#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
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#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
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#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
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#define ZPCI_TABLE_BITS 11
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#define ZPCI_PT_BITS 8
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#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + TARGET_PAGE_BITS)
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#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
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#define ZPCI_RTE_FLAG_MASK 0x3fffULL
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#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
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#define ZPCI_STE_FLAG_MASK 0x7ffULL
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#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
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#define ZPCI_SFAA_MASK (~((1ULL << 20) - 1))
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/* I/O Page tables */
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#define ZPCI_PTE_VALID_MASK 0x400
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#define ZPCI_PTE_INVALID 0x400
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#define ZPCI_PTE_VALID 0x000
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#define ZPCI_PT_SIZE 0x800
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#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
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#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
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#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
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#define ZPCI_PTE_FLAG_MASK 0xfffULL
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#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
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/* Shared bits */
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#define ZPCI_TABLE_VALID 0x00
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#define ZPCI_TABLE_INVALID 0x20
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#define ZPCI_TABLE_PROTECTED 0x200
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#define ZPCI_TABLE_UNPROTECTED 0x000
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#define ZPCI_TABLE_FC 0x400
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#define ZPCI_TABLE_VALID_MASK 0x20
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#define ZPCI_TABLE_PROT_MASK 0x200
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#define ZPCI_ETT_RT 1
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#define ZPCI_ETT_ST 0
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#define ZPCI_ETT_PT -1
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/* PCI Function States
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*
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* reserved: default; device has just been plugged or is in progress of being
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* unplugged
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* standby: device is present but not configured; transition from any
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* configured state/to this state via sclp configure/deconfigure
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*
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* The following states make up the "configured" meta-state:
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* disabled: device is configured but not enabled; transition between this
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* state and enabled via clp enable/disable
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* enbaled: device is ready for use; transition to disabled via clp disable;
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* may enter an error state
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* blocked: ignore all DMA and interrupts; transition back to enabled or from
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* error state via mpcifc
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* error: an error occurred; transition back to enabled via mpcifc
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* permanent error: an unrecoverable error occurred; transition to standby via
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* sclp deconfigure
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*/
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typedef enum {
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ZPCI_FS_RESERVED,
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ZPCI_FS_STANDBY,
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ZPCI_FS_DISABLED,
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ZPCI_FS_ENABLED,
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ZPCI_FS_BLOCKED,
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ZPCI_FS_ERROR,
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ZPCI_FS_PERMANENT_ERROR,
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} ZpciState;
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typedef struct SeiContainer {
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QTAILQ_ENTRY(SeiContainer) link;
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uint32_t fid;
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uint32_t fh;
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uint8_t cc;
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uint16_t pec;
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uint64_t faddr;
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uint32_t e;
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} SeiContainer;
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typedef struct PciCcdfErr {
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uint32_t reserved1;
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uint32_t fh;
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uint32_t fid;
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uint32_t e;
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uint64_t faddr;
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uint32_t reserved3;
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uint16_t reserved4;
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uint16_t pec;
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} QEMU_PACKED PciCcdfErr;
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typedef struct PciCcdfAvail {
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uint32_t reserved1;
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uint32_t fh;
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uint32_t fid;
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uint32_t reserved2;
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uint32_t reserved3;
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uint32_t reserved4;
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uint32_t reserved5;
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uint16_t reserved6;
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uint16_t pec;
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} QEMU_PACKED PciCcdfAvail;
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typedef struct ChscSeiNt2Res {
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uint16_t length;
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uint16_t code;
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uint16_t reserved1;
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uint8_t reserved2;
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uint8_t nt;
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uint8_t flags;
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uint8_t reserved3;
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uint8_t reserved4;
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uint8_t cc;
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uint32_t reserved5[13];
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uint8_t ccdf[4016];
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} QEMU_PACKED ChscSeiNt2Res;
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typedef struct S390MsixInfo {
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uint8_t table_bar;
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uint8_t pba_bar;
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uint16_t entries;
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uint32_t table_offset;
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uint32_t pba_offset;
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} S390MsixInfo;
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typedef struct S390IOTLBEntry {
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uint64_t iova;
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uint64_t translated_addr;
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uint64_t len;
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uint64_t perm;
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} S390IOTLBEntry;
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typedef struct S390PCIDMACount {
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int id;
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int users;
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uint32_t avail;
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QTAILQ_ENTRY(S390PCIDMACount) link;
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} S390PCIDMACount;
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struct S390PCIIOMMU {
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Object parent_obj;
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S390PCIBusDevice *pbdev;
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AddressSpace as;
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MemoryRegion mr;
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IOMMUMemoryRegion iommu_mr;
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bool enabled;
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uint64_t g_iota;
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uint64_t pba;
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uint64_t pal;
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GHashTable *iotlb;
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S390PCIDMACount *dma_limit;
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};
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typedef struct S390PCIIOMMUTable {
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uint64_t key;
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S390PCIIOMMU *iommu[PCI_SLOT_MAX];
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} S390PCIIOMMUTable;
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/* Function Measurement Block */
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#define DEFAULT_MUI 4000
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#define UPDATE_U_BIT 0x1ULL
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#define FMBK_MASK 0xfULL
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typedef struct ZpciFmbFmt0 {
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uint64_t dma_rbytes;
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uint64_t dma_wbytes;
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} ZpciFmbFmt0;
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#define ZPCI_FMB_CNT_LD 0
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#define ZPCI_FMB_CNT_ST 1
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#define ZPCI_FMB_CNT_STB 2
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#define ZPCI_FMB_CNT_RPCIT 3
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#define ZPCI_FMB_CNT_MAX 4
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#define ZPCI_FMB_FORMAT 0
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typedef struct ZpciFmb {
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uint32_t format;
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uint32_t sample;
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uint64_t last_update;
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uint64_t counter[ZPCI_FMB_CNT_MAX];
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ZpciFmbFmt0 fmt0;
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} ZpciFmb;
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QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb");
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#define ZPCI_DEFAULT_FN_GRP 0x20
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typedef struct S390PCIGroup {
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ClpRspQueryPciGrp zpci_group;
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int id;
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QTAILQ_ENTRY(S390PCIGroup) link;
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} S390PCIGroup;
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S390PCIGroup *s390_group_create(int id);
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S390PCIGroup *s390_group_find(int id);
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struct S390PCIBusDevice {
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DeviceState qdev;
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PCIDevice *pdev;
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ZpciState state;
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char *target;
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uint16_t uid;
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uint32_t idx;
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uint32_t fh;
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uint32_t fid;
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bool fid_defined;
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uint64_t fmb_addr;
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ZpciFmb fmb;
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QEMUTimer *fmb_timer;
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uint8_t isc;
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uint16_t noi;
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uint16_t maxstbl;
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uint8_t sum;
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S390PCIGroup *pci_group;
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ClpRspQueryPci zpci_fn;
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S390MsixInfo msix;
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AdapterRoutes routes;
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S390PCIIOMMU *iommu;
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MemoryRegion msix_notify_mr;
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IndAddr *summary_ind;
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IndAddr *indicator;
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bool pci_unplug_request_processed;
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bool unplug_requested;
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QTAILQ_ENTRY(S390PCIBusDevice) link;
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};
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struct S390PCIBus {
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BusState qbus;
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};
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struct S390pciState {
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PCIHostState parent_obj;
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uint32_t next_idx;
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int bus_no;
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S390PCIBus *bus;
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GHashTable *iommu_table;
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GHashTable *zpci_table;
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QTAILQ_HEAD(, SeiContainer) pending_sei;
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QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
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QTAILQ_HEAD(, S390PCIDMACount) zpci_dma_limit;
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QTAILQ_HEAD(, S390PCIGroup) zpci_groups;
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};
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S390pciState *s390_get_phb(void);
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int pci_chsc_sei_nt2_get_event(void *res);
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int pci_chsc_sei_nt2_have_event(void);
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void s390_pci_sclp_configure(SCCB *sccb);
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void s390_pci_sclp_deconfigure(SCCB *sccb);
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void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
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void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
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void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
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uint64_t faddr, uint32_t e);
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uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
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S390IOTLBEntry *entry);
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S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx);
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S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh);
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S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid);
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S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s,
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const char *target);
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S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
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S390PCIBusDevice *pbdev);
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#endif
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