Alistair Francis 8903bf6e6d target/riscv: Add a base 32 and 64 bit CPU ... At the same time deprecate the ISA string CPUs. It is dobtful anyone specifies the CPUs, but we are keeping them for the Spike machine (which is about to be depreated) so we may as well just mark them as deprecated. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-05-24 12:09:23 -07:00
..
riscv_hart.h	RISC-V HART Array	2018-03-07 08:30:28 +13:00
riscv_htif.h	…
sifive_clint.h	RISC-V: Replace hardcoded constants with enum values	2018-05-06 10:39:38 +12:00
sifive_e.h	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
sifive_gpio.h	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
sifive_plic.h	Clean up decorations and whitespace around header guards	2019-05-13 08:58:55 +02:00
sifive_prci.h	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.h	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.h	riscv: plic: Fix incorrect irq calculation	2019-04-04 16:36:19 -07:00
sifive_uart.h	sifive_uart: Implement interrupt pending register	2018-12-20 12:08:43 -08:00
spike.h	RISC-V: Make some header guards more specific	2018-05-06 10:39:38 +12:00
virt.h	target/riscv: Add a base 32 and 64 bit CPU	2019-05-24 12:09:23 -07:00